piso.tan.qmsg

来自「FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl」· QMSG 代码 · 共 17 行 · 第 1/4 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 28 21:18:50 2005 " "Info: Processing started: Sun Aug 28 21:18:50 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off piso -c piso --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off piso -c piso --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 8 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node altera_internal_jtag~TCKUTAP is an undefined clock" {  } { { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "load " "Info: Assuming node load is an undefined clock" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 9 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "load" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "sck " "Info: Assuming node sck is an undefined clock" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 8 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sck" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "pf:s1\|flag " "Info: Detected ripple clock pf:s1\|flag as buffer" {  } { { "G:/EDA/piso/pf.vhd" "" "" { Text "G:/EDA/piso/pf.vhd" 29 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "pf:s1\|flag" } } } }  } 0}  } {  } 0}