piso.map.qmsg

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "sld_dffex-DFFEX" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "sld_dffex" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "pf:s1\|yout pf:s1\|flag " "Info: Duplicate register pf:s1\|yout merged to single register pf:s1\|flag, power-up level changed" {  } { { "G:/EDA/piso/pf.vhd" "" "" { Text "G:/EDA/piso/pf.vhd" 7 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "pf:s1\|f pf:s1\|flag " "Info: Duplicate register pf:s1\|f merged to single register pf:s1\|flag, power-up level changed" {  } { { "G:/EDA/piso/pf.vhd" "" "" { Text "G:/EDA/piso/pf.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add:s4\|temp\[7\] data_in GND " "Warning: Reduced register add:s4\|temp\[7\] with stuck data_in port to stuck value GND" {  } { { "F:/zhf/piso/add.vhd" "" "" { Text "F:/zhf/piso/add.vhd" 21 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add:s4\|temp\[8\] data_in GND " "Warning: Reduced register add:s4\|temp\[8\] with stuck data_in port to stuck value GND" {  } { { "F:/zhf/piso/add.vhd" "" "" { Text "F:/zhf/piso/add.vhd" 21 -1 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "piso:s2\|i\[0\]~0 5 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: piso:s2\|i\[0\]~0" {  } { { "F:/EDA/piso/piso.vhd" "" "i\[0\]~0" { Text "F:/EDA/piso/piso.vhd" 21 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "sin_rom:s3\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~360 9 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: sin_rom:s3\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~360" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "ram_rom_addr_reg\[0\]~360" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 394 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "sin_rom:s3\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_shift_cntr_reg\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: sin_rom:s3\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_shift_cntr_reg\[0\]~8" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "ram_rom_data_shift_cntr_reg\[0\]~8" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 537 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~360 9 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~360" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "ram_rom_addr_reg\[0\]~360" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 394 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_shift_cntr_reg\[0\]~8 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: sin_rom:s5\|altsyncram:altsyncram_component\|altsyncram_qjs:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_data_shift_cntr_reg\[0\]~8" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "ram_rom_data_shift_cntr_reg\[0\]~8" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 537 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "e:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "e:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_fa7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_fa7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_fa7 " "Info: Found entity 1: cntr_fa7" {  } { { "G:/EDA/piso/db/cntr_fa7.tdf" "cntr_fa7" "" { Text "G:/EDA/piso/db/cntr_fa7.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_0a8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_0a8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_0a8 " "Info: Found entity 1: cntr_0a8" {  } { { "G:/EDA/piso/db/cntr_0a8.tdf" "cntr_0a8" "" { Text "G:/EDA/piso/db/cntr_0a8.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_pd8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_pd8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_pd8 " "Info: Found entity 1: cntr_pd8" {  } { { "G:/EDA/piso/db/cntr_pd8.tdf" "cntr_pd8" "" { Text "G:/EDA/piso/db/cntr_pd8.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "st\[8\] GND " "Warning: Pin st\[8\] stuck at GND" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "st\[7\] GND " "Warning: Pin st\[7\] stuck at GND" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "st\[6\] GND " "Warning: Pin st\[6\] stuck at GND" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "st\[5\] GND " "Warning: Pin st\[5\] stuck at GND" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "st\[4\] GND " "Warning: Pin st\[4\] stuck at GND" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "st\[3\] GND " "Warning: Pin st\[3\] stuck at GND" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "st\[2\] GND " "Warning: Pin st\[2\] stuck at GND" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "st\[1\] GND " "Warning: Pin st\[1\] stuck at GND" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "st\[0\] GND " "Warning: Pin st\[0\] stuck at GND" {  } { { "G:/EDA/piso/top.vhd" "" "" { Text "G:/EDA/piso/top.vhd" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "522 " "Info: Implemented 522 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "27 " "Info: Implemented 27 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "471 " "Info: Implemented 471 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 28 21:18:26 2005 " "Info: Processing ended: Sun Aug 28 21:18:26 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0}  } {  } 0}