piso.map.rpt

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

; Total fan-out                     ; 2154                     ;
; Average fan-out                   ; 4.13                     ;
+-----------------------------------+--------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                ;
+-----------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+--------------------+
; Name                                                                                                            ; Type ; Mode           ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF                ;
+-----------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+--------------------+
; sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 512          ; 8            ; 512          ; 8            ; 4096 ; ./DATA/sin_rom.mif ;
; sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 512          ; 8            ; 512          ; 8            ; 4096 ; ./DATA/sin_rom.mif ;
+-----------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+--------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sun Aug 28 21:18:12 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off piso -c piso
Info: Found 2 design units, including 1 entities, in source file sin_rom.vhd
    Info: Found design unit 1: sin_rom-SYN
    Info: Found entity 1: sin_rom
Info: Found 2 design units, including 1 entities, in source file piso.vhd
    Info: Found design unit 1: piso-behave
    Info: Found entity 1: piso
Info: Found 2 design units, including 1 entities, in source file pf.vhd
    Info: Found design unit 1: pf-pf_1024
    Info: Found entity 1: pf
Info: Found 2 design units, including 1 entities, in source file top.vhd
    Info: Found design unit 1: top-top_1
    Info: Found entity 1: top
Info: Found 2 design units, including 1 entities, in source file add.vhd
    Info: Found design unit 1: add-add_n
    Info: Found entity 1: add
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_qjs.tdf
    Info: Found entity 1: altsyncram_qjs
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gaa2.tdf
    Info: Found entity 1: altsyncram_gaa2
Info: Found 3 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd
    Info: Found design unit 1: sld_mod_ram_rom_pack
    Info: Found design unit 2: sld_mod_ram_rom-rtl
    Info: Found entity 1: sld_mod_ram_rom
Info: Found 2 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Info: Found 6 design units, including 2 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd
    Info: Found design unit 1: HUB_PACK
    Info: Found design unit 2: JTAG_PACK
    Info: Found design unit 3: sld_hub-rtl
    Info: Found design unit 4: sld_jtag_state_machine-rtl
    Info: Found entity 1: sld_hub
    Info: Found entity 2: sld_jtag_state_machine
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf
    Info: Found entity 1: lpm_decode
Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf
    Info: Found entity 1: decode_9ie
Info: Found 2 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd
    Info: Found design unit 1: sld_dffex-DFFEX
    Info: Found entity 1: sld_dffex
Info: Duplicate registers merged to single register
    Info: Duplicate register pf:s1|yout merged to single register pf:s1|flag, power-up level changed
    Info: Duplicate register pf:s1|f merged to single register pf:s1|flag, power-up level changed
Warning: Reduced register add:s4|temp[7] with stuck data_in port to stuck value GND
Warning: Reduced register add:s4|temp[8] with stuck data_in port to stuck value GND
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: piso:s2|i[0]~0
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~360
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]~8
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~360
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]~8
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_fa7.tdf
    Info: Found entity 1: cntr_fa7
Info: Found 1 design units, including 1 entities, in source file db/cntr_0a8.tdf
    Info: Found entity 1: cntr_0a8
Info: Found 1 design units, including 1 entities, in source file db/cntr_pd8.tdf
    Info: Found entity 1: cntr_pd8
Warning: Output pins are stuck at VCC or GND
    Warning: Pin st[8] stuck at GND
    Warning: Pin st[7] stuck at GND
    Warning: Pin st[6] stuck at GND
    Warning: Pin st[5] stuck at GND
    Warning: Pin st[4] stuck at GND
    Warning: Pin st[3] stuck at GND
    Warning: Pin st[2] stuck at GND
    Warning: Pin st[1] stuck at GND
    Warning: Pin st[0] stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 522 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 27 output pins
    Info: Implemented 471 logic cells
    Info: Implemented 16 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Processing ended: Sun Aug 28 21:18:26 2005
    Info: Elapsed time: 00:00:14