📄 piso.map.rpt
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (No Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 2:1 ; 3 bits ; 3 LEs ; 3 LEs ; 0 LEs ; Yes ; |top|add:s4|temp[4] ;
; 2:1 ; 2 bits ; 2 LEs ; 2 LEs ; 0 LEs ; Yes ; |top|add:s4|sinout[7] ;
; 2:1 ; 5 bits ; 5 LEs ; 5 LEs ; 0 LEs ; Yes ; |top|add:s4|sinout[2] ;
; 2:1 ; 4 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |top|add:s4|temp[6] ;
; 2:1 ; 4 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |top|sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ;
; 3:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |top|sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |top|sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ;
; 14:1 ; 4 bits ; 36 LEs ; 24 LEs ; 12 LEs ; Yes ; |top|sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ;
; 2:1 ; 4 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |top|sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0] ;
; 3:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |top|sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8] ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |top|sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ;
; 14:1 ; 4 bits ; 36 LEs ; 24 LEs ; 12 LEs ; Yes ; |top|sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0] ;
; 2:1 ; 10 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |top|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[2] ;
; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |top|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] ;
; 26:1 ; 4 bits ; 68 LEs ; 40 LEs ; 28 LEs ; Yes ; |top|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] ;
; 2:1 ; 2 bits ; 2 LEs ; 2 LEs ; 0 LEs ; No ; |top|sld_hub:sld_hub_inst|NODE_ENA~0 ;
; 2:1 ; 2 bits ; 2 LEs ; 2 LEs ; 0 LEs ; No ; |top|sld_hub:sld_hub_inst|SHADOW_IRF_ENABLE[2] ;
; 2:1 ; 2 bits ; 2 LEs ; 2 LEs ; 0 LEs ; No ; |top|sld_hub:sld_hub_inst|IR_MUX_SEL[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+--------------------------------------------------------+-------+
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 105 ;
; Number of synthesis-generated cells ; 366 ;
; Number of WYSIWYG LUTs ; 105 ;
; Number of synthesis-generated LUTs ; 231 ;
; Number of WYSIWYG registers ; 59 ;
; Number of synthesis-generated registers ; 210 ;
; Number of cells with combinational logic only ; 202 ;
; Number of cells with registers only ; 135 ;
; Number of cells with combinational logic and registers ; 134 ;
+--------------------------------------------------------+-------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear ; 8 ;
; Number of registers using Synchronous Load ; 46 ;
; Number of registers using Asynchronous Clear ; 118 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 189 ;
; Number of registers using Output Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------+
; In-System Memory Content Editor Setting ;
+----------------+-------------+-------+-------+------------+-------------------------------------------------------------------------------+
; Instance Index ; Instance ID ; Width ; Depth ; Mode ; Hierarchy Location ;
+----------------+-------------+-------+-------+------------+-------------------------------------------------------------------------------+
; 0 ; NONE ; 8 ; 512 ; Read/Write ; |top|sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated ;
; 1 ; NONE ; 8 ; 512 ; Read/Write ; |top|sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated ;
+----------------+-------------+-------+-------+------------+-------------------------------------------------------------------------------+
+-----------+
; Hierarchy ;
+-----------+
top
|-- pf:s1
|-- piso:s2
|-- lpm_counter:i_rtl_0
|-- cntr_fa7:auto_generated
|-- sin_rom:s3
|-- altsyncram:altsyncram_component
|-- altsyncram_qjs:auto_generated
|-- altsyncram_gaa2:altsyncram1
|-- sld_mod_ram_rom:mgl_prim2
|-- sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr
|-- lpm_counter:ram_rom_addr_reg_rtl_0
|-- cntr_0a8:auto_generated
|-- lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1
|-- cntr_pd8:auto_generated
|-- add:s4
|-- sin_rom:s5
|-- altsyncram:altsyncram_component
|-- altsyncram_qjs:auto_generated
|-- altsyncram_gaa2:altsyncram1
|-- sld_mod_ram_rom:mgl_prim2
|-- sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr
|-- lpm_counter:ram_rom_addr_reg_rtl_0
|-- cntr_0a8:auto_generated
|-- lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1
|-- cntr_pd8:auto_generated
|-- sld_hub:sld_hub_inst
|-- sld_dffex:\GEN_IRF:1:IRF
|-- sld_dffex:\GEN_IRF:2:IRF
|-- sld_dffex:\GEN_SHADOW_IRF:1:S_IRF
|-- sld_dffex:\GEN_SHADOW_IRF:2:S_IRF
|-- sld_dffex:BROADCAST
|-- sld_rom_sr:HUB_INFO_REG
|-- lpm_decode:instruction_decoder
|-- decode_9ie:auto_generated
|-- sld_dffex:IRF_ENA
|-- sld_dffex:IRF_ENA_0
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