piso.fit.eqn

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

--B1_\P1:cnt[15] is pf:s1|\P1:cnt[15] at LC_X15_Y6_N4
--operation mode is normal

B1_\P1:cnt[15]_sload_eqn = B1_b[15];
B1_\P1:cnt[15] = DFFEA(B1_\P1:cnt[15]_sload_eqn, GLOBAL(clk), VCC, , B1L93, , );


--B1_\P1:cnt[10] is pf:s1|\P1:cnt[10] at LC_X15_Y5_N8
--operation mode is normal

B1_\P1:cnt[10]_sload_eqn = B1_b[10];
B1_\P1:cnt[10] = DFFEA(B1_\P1:cnt[10]_sload_eqn, GLOBAL(clk), VCC, , B1L93, , );


--B1_\P1:cnt[9] is pf:s1|\P1:cnt[9] at LC_X15_Y5_N2
--operation mode is normal

B1_\P1:cnt[9]_lut_out = B1_b[9];
B1_\P1:cnt[9] = DFFEA(B1_\P1:cnt[9]_lut_out, GLOBAL(clk), VCC, , B1L93, , );


--B1_\P1:cnt[8] is pf:s1|\P1:cnt[8] at LC_X15_Y5_N1
--operation mode is normal

B1_\P1:cnt[8]_sload_eqn = B1_b[8];
B1_\P1:cnt[8] = DFFEA(B1_\P1:cnt[8]_sload_eqn, GLOBAL(clk), VCC, , B1L93, , );


--B1L63 is pf:s1|reduce_nor~125 at LC_X15_Y6_N8
--operation mode is normal

B1_\P1:cnt[11]_qfbk = B1_\P1:cnt[11];
B1L63 = !B1_\P1:cnt[8] # !B1_\P1:cnt[11]_qfbk # !B1_\P1:cnt[10] # !B1_\P1:cnt[9];

--B1_\P1:cnt[11] is pf:s1|\P1:cnt[11] at LC_X15_Y6_N8
--operation mode is normal

B1_\P1:cnt[11]_sload_eqn = B1_b[11];
B1_\P1:cnt[11] = DFFEA(B1_\P1:cnt[11]_sload_eqn, GLOBAL(clk), VCC, , B1L93, , );


--B1_\P1:cnt[6] is pf:s1|\P1:cnt[6] at LC_X8_Y6_N4
--operation mode is normal

B1_\P1:cnt[6]_lut_out = B1_b[6];
B1_\P1:cnt[6] = DFFEA(B1_\P1:cnt[6]_lut_out, GLOBAL(clk), VCC, , B1L93, , );


--B1_\P1:cnt[5] is pf:s1|\P1:cnt[5] at LC_X15_Y6_N0
--operation mode is normal

B1_\P1:cnt[5]_sload_eqn = B1_b[5];
B1_\P1:cnt[5] = DFFEA(B1_\P1:cnt[5]_sload_eqn, GLOBAL(clk), VCC, , B1L93, , );


--B1_\P1:cnt[4] is pf:s1|\P1:cnt[4] at LC_X8_Y6_N8
--operation mode is normal

B1_\P1:cnt[4]_sload_eqn = B1_b[4];
B1_\P1:cnt[4] = DFFEA(B1_\P1:cnt[4]_sload_eqn, GLOBAL(clk), VCC, , B1L93, , );


--B1L73 is pf:s1|reduce_nor~126 at LC_X15_Y6_N1
--operation mode is normal

B1_\P1:cnt[7]_qfbk = B1_\P1:cnt[7];
B1L73 = !B1_\P1:cnt[5] # !B1_\P1:cnt[7]_qfbk # !B1_\P1:cnt[4] # !B1_\P1:cnt[6];

--B1_\P1:cnt[7] is pf:s1|\P1:cnt[7] at LC_X15_Y6_N1
--operation mode is normal

B1_\P1:cnt[7]_sload_eqn = B1_b[7];
B1_\P1:cnt[7] = DFFEA(B1_\P1:cnt[7]_sload_eqn, GLOBAL(clk), VCC, , B1L93, , );


--B1_\P1:cnt[2] is pf:s1|\P1:cnt[2] at LC_X15_Y6_N6
--operation mode is normal

B1_\P1:cnt[2]_sload_eqn = B1_b[2];
B1_\P1:cnt[2] = DFFEA(B1_\P1:cnt[2]_sload_eqn, GLOBAL(clk), VCC, , B1L93, , );


--B1_\P1:cnt[1] is pf:s1|\P1:cnt[1] at LC_X8_Y6_N5
--operation mode is normal

B1_\P1:cnt[1]_sload_eqn = B1_b[1];
B1_\P1:cnt[1] = DFFEA(B1_\P1:cnt[1]_sload_eqn, GLOBAL(clk), VCC, , B1L93, , );


--B1_\P1:cnt[0] is pf:s1|\P1:cnt[0] at LC_X15_Y6_N5
--operation mode is normal

B1_\P1:cnt[0]_lut_out = B1_b[0];
B1_\P1:cnt[0] = DFFEA(B1_\P1:cnt[0]_lut_out, GLOBAL(clk), VCC, , B1L93, , );


--B1L83 is pf:s1|reduce_nor~127 at LC_X15_Y6_N7
--operation mode is normal

B1_\P1:cnt[3]_qfbk = B1_\P1:cnt[3];
B1L83 = !B1_\P1:cnt[2] # !B1_\P1:cnt[3]_qfbk # !B1_\P1:cnt[0] # !B1_\P1:cnt[1];

--B1_\P1:cnt[3] is pf:s1|\P1:cnt[3] at LC_X15_Y6_N7
--operation mode is normal

B1_\P1:cnt[3]_sload_eqn = B1_b[3];
B1_\P1:cnt[3] = DFFEA(B1_\P1:cnt[3]_sload_eqn, GLOBAL(clk), VCC, , B1L93, , );


--B1L93 is pf:s1|reduce_nor~128 at LC_X15_Y6_N9
--operation mode is normal

B1L93 = !B1L73 & !B1L53 & !B1L83 & !B1L63;


--R1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] at LC_X18_Y12_N6
--operation mode is normal

R1_Q[2] = AMPP_FUNCTION(A1L5, R3_Q[2], R5_Q[0], R8_Q[2], !F1L2, F1L43);


--M1L23 is sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~1 at LC_X18_Y12_N4
--operation mode is normal

M1L23 = AMPP_FUNCTION(R1_Q[2]);

--M1_ram_rom_incr_write_addr_reg is sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_write_addr_reg at LC_X18_Y12_N4
--operation mode is normal

M1_ram_rom_incr_write_addr_reg = AMPP_FUNCTION(A1L5, M1_ram_rom_load_read_data, VCC, GND);


--E1_sinout[2] is add:s4|sinout[2] at LC_X15_Y10_N1
--operation mode is arithmetic

E1_sinout[2]_lut_out = !E1L5;
E1_sinout[2]_sload_eqn = (E1L671 & E1L5) # (!E1L671 & E1_sinout[2]_lut_out);
E1_sinout[2] = DFFEA(E1_sinout[2]_sload_eqn, !GLOBAL(B1_flag), VCC, , E1L191, , );

--E1L991 is add:s4|sinout[2]~COUT0 at LC_X15_Y10_N1
--operation mode is arithmetic

E1L991_cout_0 = E1L5;
E1L991 = CARRY(E1L991_cout_0);

--E1L002 is add:s4|sinout[2]~COUT1 at LC_X15_Y10_N1
--operation mode is arithmetic

E1L002_cout_1 = E1L5;
E1L002 = CARRY(E1L002_cout_1);


--E1_sinout[3] is add:s4|sinout[3] at LC_X15_Y10_N2
--operation mode is arithmetic

E1_sinout[3]_lut_out = E1L9 $ !E1L991;
E1_sinout[3]_sload_eqn = (E1L671 & E1L9) # (!E1L671 & E1_sinout[3]_lut_out);
E1_sinout[3] = DFFEA(E1_sinout[3]_sload_eqn, !GLOBAL(B1_flag), VCC, , E1L191, , );

--E1L302 is add:s4|si