piso.fit.eqn

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

L2_q_b[7]_PORT_B_data_in_reg = DFFE(L2_q_b[7]_PORT_B_data_in, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_b[7]_PORT_A_address_reg = DFFE(L2_q_b[7]_PORT_A_address, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_b[7]_PORT_B_address_reg = DFFE(L2_q_b[7]_PORT_B_address, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_PORT_A_write_enable = GND;
L2_q_b[7]_PORT_A_write_enable_reg = DFFE(L2_q_b[7]_PORT_A_write_enable, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_write_enable = M2L23;
L2_q_b[7]_PORT_B_write_enable_reg = DFFE(L2_q_b[7]_PORT_B_write_enable, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_clock_0 = GLOBAL(clk);
L2_q_b[7]_clock_1 = GLOBAL(A1L5);
L2_q_b[7]_PORT_B_data_out = MEMORY(L2_q_b[7]_PORT_A_data_in_reg, L2_q_b[7]_PORT_B_data_in_reg, L2_q_b[7]_PORT_A_address_reg, L2_q_b[7]_PORT_B_address_reg, L2_q_b[7]_PORT_A_write_enable_reg, L2_q_b[7]_PORT_B_write_enable_reg, , , L2_q_b[7]_clock_0, L2_q_b[7]_clock_1, , , , );
L2_q_b[0] = L2_q_b[7]_PORT_B_data_out[7];

--L2_q_b[1] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_b[1] at M4K_X13_Y8
L2_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
L2_q_b[7]_PORT_A_data_in_reg = DFFE(L2_q_b[7]_PORT_A_data_in, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_data_in = BUS(M2_ram_rom_data_reg[7], M2_ram_rom_data_reg[6], M2_ram_rom_data_reg[5], M2_ram_rom_data_reg[4], M2_ram_rom_data_reg[3], M2_ram_rom_data_reg[2], M2_ram_rom_data_reg[1], M2_ram_rom_data_reg[0]);
L2_q_b[7]_PORT_B_data_in_reg = DFFE(L2_q_b[7]_PORT_B_data_in, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_b[7]_PORT_A_address_reg = DFFE(L2_q_b[7]_PORT_A_address, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_b[7]_PORT_B_address_reg = DFFE(L2_q_b[7]_PORT_B_address, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_PORT_A_write_enable = GND;
L2_q_b[7]_PORT_A_write_enable_reg = DFFE(L2_q_b[7]_PORT_A_write_enable, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_write_enable = M2L23;
L2_q_b[7]_PORT_B_write_enable_reg = DFFE(L2_q_b[7]_PORT_B_write_enable, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_clock_0 = GLOBAL(clk);
L2_q_b[7]_clock_1 = GLOBAL(A1L5);
L2_q_b[7]_PORT_B_data_out = MEMORY(L2_q_b[7]_PORT_A_data_in_reg, L2_q_b[7]_PORT_B_data_in_reg, L2_q_b[7]_PORT_A_address_reg, L2_q_b[7]_PORT_B_address_reg, L2_q_b[7]_PORT_A_write_enable_reg, L2_q_b[7]_PORT_B_write_enable_reg, , , L2_q_b[7]_clock_0, L2_q_b[7]_clock_1, , , , );
L2_q_b[1] = L2_q_b[7]_PORT_B_data_out[6];

--L2_q_b[2] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_b[2] at M4K_X13_Y8
L2_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
L2_q_b[7]_PORT_A_data_in_reg = DFFE(L2_q_b[7]_PORT_A_data_in, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_data_in = BUS(M2_ram_rom_data_reg[7], M2_ram_rom_data_reg[6], M2_ram_rom_data_reg[5], M2_ram_rom_data_reg[4], M2_ram_rom_data_reg[3], M2_ram_rom_data_reg[2], M2_ram_rom_data_reg[1], M2_ram_rom_data_reg[0]);
L2_q_b[7]_PORT_B_data_in_reg = DFFE(L2_q_b[7]_PORT_B_data_in, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_b[7]_PORT_A_address_reg = DFFE(L2_q_b[7]_PORT_A_address, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_b[7]_PORT_B_address_reg = DFFE(L2_q_b[7]_PORT_B_address, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_PORT_A_write_enable = GND;
L2_q_b[7]_PORT_A_write_enable_reg = DFFE(L2_q_b[7]_PORT_A_write_enable, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_write_enable = M2L23;
L2_q_b[7]_PORT_B_write_enable_reg = DFFE(L2_q_b[7]_PORT_B_write_enable, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_clock_0 = GLOBAL(clk);
L2_q_b[7]_clock_1 = GLOBAL(A1L5);
L2_q_b[7]_PORT_B_data_out = MEMORY(L2_q_b[7]_PORT_A_data_in_reg, L2_q_b[7]_PORT_B_data_in_reg, L2_q_b[7]_PORT_A_address_reg, L2_q_b[7]_PORT_B_address_reg, L2_q_b[7]_PORT_A_write_enable_reg, L2_q_b[7]_PORT_B_write_enable_reg, , , L2_q_b[7]_clock_0, L2_q_b[7]_clock_1, , , , );
L2_q_b[2] = L2_q_b[7]_PORT_B_data_out[5];

--L2_q_b[3] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_b[3] at M4K_X13_Y8
L2_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
L2_q_b[7]_PORT_A_data_in_reg = DFFE(L2_q_b[7]_PORT_A_data_in, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_data_in = BUS(M2_ram_rom_data_reg[7], M2_ram_rom_data_reg[6], M2_ram_rom_data_reg[5], M2_ram_rom_data_reg[4], M2_ram_rom_data_reg[3], M2_ram_rom_data_reg[2], M2_ram_rom_data_reg[1], M2_ram_rom_data_reg[0]);
L2_q_b[7]_PORT_B_data_in_reg = DFFE(L2_q_b[7]_PORT_B_data_in, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_b[7]_PORT_A_address_reg = DFFE(L2_q_b[7]_PORT_A_address, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_b[7]_PORT_B_address_reg = DFFE(L2_q_b[7]_PORT_B_address, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_PORT_A_write_enable = GND;
L2_q_b[7]_PORT_A_write_enable_reg = DFFE(L2_q_b[7]_PORT_A_write_enable, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_write_enable = M2L23;
L2_q_b[7]_PORT_B_write_enable_reg = DFFE(L2_q_b[7]_PORT_B_write_enable, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_clock_0 = GLOBAL(clk);
L2_q_b[7]_clock_1 = GLOBAL(A1L5);
L2_q_b[7]_PORT_B_data_out = MEMORY(L2_q_b[7]_PORT_A_data_in_reg, L2_q_b[7]_PORT_B_data_in_reg, L2_q_b[7]_PORT_A_address_reg, L2_q_b[7]_PORT_B_address_reg, L2_q_b[7]_PORT_A_write_enable_reg, L2_q_b[7]_PORT_B_write_enable_reg, , , L2_q_b[7]_clock_0, L2_q_b[7]_clock_1, , , , );
L2_q_b[3] = L2_q_b[7]_PORT_B_data_out[4];

--L2_q_b[4] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_b[4] at M4K_X13_Y8
L2_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
L2_q_b[7]_PORT_A_data_in_reg = DFFE(L2_q_b[7]_PORT_A_data_in, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_data_in = BUS(M2_ram_rom_data_reg[7], M2_ram_rom_data_reg[6], M2_ram_rom_data_reg[5], M2_ram_rom_data_reg[4], M2_ram_rom_data_reg[3], M2_ram_rom_data_reg[2], M2_ram_rom_data_reg[1], M2_ram_rom_data_reg[0]);
L2_q_b[7]_PORT_B_data_in_reg = DFFE(L2_q_b[7]_PORT_B_data_in, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_b[7]_PORT_A_address_reg = DFFE(L2_q_b[7]_PORT_A_address, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_b[7]_PORT_B_address_reg = DFFE(L2_q_b[7]_PORT_B_address, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_PORT_A_write_enable = GND;
L2_q_b[7]_PORT_A_write_enable_reg = DFFE(L2_q_b[7]_PORT_A_write_enable, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_write_enable = M2L23;
L2_q_b[7]_PORT_B_write_enable_reg = DFFE(L2_q_b[7]_PORT_B_write_enable, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_clock_0 = GLOBAL(clk);
L2_q_b[7]_clock_1 = GLOBAL(A1L5);
L2_q_b[7]_PORT_B_data_out = MEMORY(L2_q_b[7]_PORT_A_data_in_reg, L2_q_b[7]_PORT_B_data_in_reg, L2_q_b[7]_PORT_A_address_reg, L2_q_b[7]_PORT_B_address_reg, L2_q_b[7]_PORT_A_write_enable_reg, L2_q_b[7]_PORT_B_write_enable_reg, , , L2_q_b[7]_clock_0, L2_q_b[7]_clock_1, , , , );
L2_q_b[4] = L2_q_b[7]_PORT_B_data_out[3];

--L2_q_b[5] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_b[5] at M4K_X13_Y8
L2_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
L2_q_b[7]_PORT_A_data_in_reg = DFFE(L2_q_b[7]_PORT_A_data_in, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_data_in = BUS(M2_ram_rom_data_reg[7], M2_ram_rom_data_reg[6], M2_ram_rom_data_reg[5], M2_ram_rom_data_reg[4], M2_ram_rom_data_reg[3], M2_ram_rom_data_reg[2], M2_ram_rom_data_reg[1], M2_ram_rom_data_reg[0]);
L2_q_b[7]_PORT_B_data_in_reg = DFFE(L2_q_b[7]_PORT_B_data_in, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_b[7]_PORT_A_address_reg = DFFE(L2_q_b[7]_PORT_A_address, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_b[7]_PORT_B_address_reg = DFFE(L2_q_b[7]_PORT_B_address, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_PORT_A_write_enable = GND;
L2_q_b[7]_PORT_A_write_enable_reg = DFFE(L2_q_b[7]_PORT_A_write_enable, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_write_enable = M2L23;
L2_q_b[7]_PORT_B_write_enable_reg = DFFE(L2_q_b[7]_PORT_B_write_enable, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_clock_0 = GLOBAL(clk);
L2_q_b[7]_clock_1 = GLOBAL(A1L5);
L2_q_b[7]_PORT_B_data_out = MEMORY(L2_q_b[7]_PORT_A_data_in_reg, L2_q_b[7]_PORT_B_data_in_reg, L2_q_b[7]_PORT_A_address_reg, L2_q_b[7]_PORT_B_address_reg, L2_q_b[7]_PORT_A_write_enable_reg, L2_q_b[7]_PORT_B_write_enable_reg, , , L2_q_b[7]_clock_0, L2_q_b[7]_clock_1, , , , );
L2_q_b[5] = L2_q_b[7]_PORT_B_data_out[2];

--L2_q_b[6] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_b[6] at M4K_X13_Y8
L2_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
L2_q_b[7]_PORT_A_data_in_reg = DFFE(L2_q_b[7]_PORT_A_data_in, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_data_in = BUS(M2_ram_rom_data_reg[7], M2_ram_rom_data_reg[6], M2_ram_rom_data_reg[5], M2_ram_rom_data_reg[4], M2_ram_rom_data_reg[3], M2_ram_rom_data_reg[2], M2_ram_rom_data_reg[1], M2_ram_rom_data_reg[0]);
L2_q_b[7]_PORT_B_data_in_reg = DFFE(L2_q_b[7]_PORT_B_data_in, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_b[7]_PORT_A_address_reg = DFFE(L2_q_b[7]_PORT_A_address, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_b[7]_PORT_B_address_reg = DFFE(L2_q_b[7]_PORT_B_address, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_PORT_A_write_enable = GND;
L2_q_b[7]_PORT_A_write_enable_reg = DFFE(L2_q_b[7]_PORT_A_write_enable, L2_q_b[7]_clock_0, , , );
L2_q_b[7]_PORT_B_write_enable = M2L23;
L2_q_b[7]_PORT_B_write_enable_reg = DFFE(L2_q_b[7]_PORT_B_write_enable, L2_q_b[7]_clock_1, , , );
L2_q_b[7]_clock_0 = GLOBAL(clk);
L2_q_b[7]_clock_1 = GLOBAL(A1L5);
L2_q_b[7]_PORT_B_data_out = MEMORY(L2_q_b[7]_PORT_A_data_in_reg, L2_q_b[7]_PORT_B_data_in_reg, L2_q_b[7]_PORT_A_address_reg, L2_q_b[7]_PORT_B_address_reg, L2_q_b[7]_PORT_A_write_enable_reg, L2_q_b[7]_PORT_B_write_enable_reg, , , L2_q_b[7]_clock_0, L2_q_b[7]_clock_1, , , , );
L2_q_b[6] = L2_q_b[7]_PORT_B_data_out[1];


--A1L6 is altera_internal_jtag~TDO at JTAG_X1_Y6_N1
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !F1L32Q);

--A1L7 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y6_N1
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !F1L32Q);

--A1L5 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y6_N1
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !F1L32Q);

--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y6_N1
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !F1L32Q);


--B1_\P1:cnt[14] is pf:s1|\P1:cnt[14] at LC_X15_Y6_N3
--operation mode is normal

B1_\P1:cnt[14]_sload_eqn = B1_b[14];
B1_\P1:cnt[14] = DFFEA(B1_\P1:cnt[14]_sload_eqn, GLOBAL(clk), VCC, , B1L93, , );


--B1_\P1:cnt[13] is pf:s1|\P1:cnt[13] at LC_X15_Y6_N2
--operation mode is normal

B1_\P1:cnt[13]_lut_out = B1_b[13];
B1_\P1:cnt[13] = DFFEA(B1_\P1:cnt[13]_lut_out, GLOBAL(clk), VCC, , B1L93, , );


--B1_\P1:cnt[12] is pf:s1|\P1:cnt[12] at LC_X8_Y6_N2
--operation mode is normal

B1_\P1:cnt[12]_sload_eqn = B1_b[12];
B1_\P1:cnt[12] = DFFEA(B1_\P1:cnt[12]_sload_eqn, GLOBAL(clk), VCC, , B1L93, , );


--B1L53 is pf:s1|reduce_nor~124 at LC_X15_Y6_N4
--operation mode is normal

B1_\P1:cnt[15]_qfbk = B1_\P1:cnt[15];
B1L53 = !B1_\P1:cnt[14] # !B1_\P1:cnt[15]_qfbk # !B1_\P1:cnt[12] # !B1_\P1:cnt[13];