piso.fit.eqn

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

--B1_flag is pf:s1|flag at LC_X8_Y6_N6
--operation mode is normal

B1_flag_lut_out = !B1_flag;
B1_flag = DFFEA(B1_flag_lut_out, GLOBAL(clk), VCC, , B1L93, , );


--L1_q_a[7] is sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[7] at M4K_X13_Y10
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 8, Port B Depth: 512, Port B Width: 8
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
L1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
L1_q_a[7]_PORT_A_data_in_reg = DFFE(L1_q_a[7]_PORT_A_data_in, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_data_in = BUS(M1_ram_rom_data_reg[7], M1_ram_rom_data_reg[6], M1_ram_rom_data_reg[5], M1_ram_rom_data_reg[4], M1_ram_rom_data_reg[3], M1_ram_rom_data_reg[2], M1_ram_rom_data_reg[1], M1_ram_rom_data_reg[0]);
L1_q_a[7]_PORT_B_data_in_reg = DFFE(L1_q_a[7]_PORT_B_data_in, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_PORT_A_address = BUS(E1_sinout[0], E1_sinout[1], E1_sinout[2], E1_sinout[3], E1_sinout[4], E1_sinout[5], E1_sinout[6], E1_sinout[7], E1_sinout[8]);
L1_q_a[7]_PORT_A_address_reg = DFFE(L1_q_a[7]_PORT_A_address, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
L1_q_a[7]_PORT_B_address_reg = DFFE(L1_q_a[7]_PORT_B_address, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_PORT_A_write_enable = GND;
L1_q_a[7]_PORT_A_write_enable_reg = DFFE(L1_q_a[7]_PORT_A_write_enable, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_write_enable = M1L23;
L1_q_a[7]_PORT_B_write_enable_reg = DFFE(L1_q_a[7]_PORT_B_write_enable, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_clock_0 = GLOBAL(clk);
L1_q_a[7]_clock_1 = GLOBAL(A1L5);
L1_q_a[7]_PORT_A_data_out = MEMORY(L1_q_a[7]_PORT_A_data_in_reg, L1_q_a[7]_PORT_B_data_in_reg, L1_q_a[7]_PORT_A_address_reg, L1_q_a[7]_PORT_B_address_reg, L1_q_a[7]_PORT_A_write_enable_reg, L1_q_a[7]_PORT_B_write_enable_reg, , , L1_q_a[7]_clock_0, L1_q_a[7]_clock_1, , , , );
L1_q_a[7]_PORT_A_data_out_reg = DFFE(L1_q_a[7]_PORT_A_data_out, L1_q_a[7]_clock_0, , , );
L1_q_a[7] = L1_q_a[7]_PORT_A_data_out_reg[0];

--L1_q_b[7] is sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_b[7] at M4K_X13_Y10
L1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
L1_q_b[7]_PORT_A_data_in_reg = DFFE(L1_q_b[7]_PORT_A_data_in, L1_q_b[7]_clock_0, , , );
L1_q_b[7]_PORT_B_data_in = BUS(M1_ram_rom_data_reg[7], M1_ram_rom_data_reg[6], M1_ram_rom_data_reg[5], M1_ram_rom_data_reg[4], M1_ram_rom_data_reg[3], M1_ram_rom_data_reg[2], M1_ram_rom_data_reg[1], M1_ram_rom_data_reg[0]);
L1_q_b[7]_PORT_B_data_in_reg = DFFE(L1_q_b[7]_PORT_B_data_in, L1_q_b[7]_clock_1, , , );
L1_q_b[7]_PORT_A_address = BUS(E1_sinout[0], E1_sinout[1], E1_sinout[2], E1_sinout[3], E1_sinout[4], E1_sinout[5], E1_sinout[6], E1_sinout[7], E1_sinout[8]);
L1_q_b[7]_PORT_A_address_reg = DFFE(L1_q_b[7]_PORT_A_address, L1_q_b[7]_clock_0, , , );
L1_q_b[7]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
L1_q_b[7]_PORT_B_address_reg = DFFE(L1_q_b[7]_PORT_B_address, L1_q_b[7]_clock_1, , , );
L1_q_b[7]_PORT_A_write_enable = GND;
L1_q_b[7]_PORT_A_write_enable_reg = DFFE(L1_q_b[7]_PORT_A_write_enable, L1_q_b[7]_clock_0, , , );
L1_q_b[7]_PORT_B_write_enable = M1L23;
L1_q_b[7]_PORT_B_write_enable_reg = DFFE(L1_q_b[7]_PORT_B_write_enable, L1_q_b[7]_clock_1, , , );
L1_q_b[7]_clock_0 = GLOBAL(clk);
L1_q_b[7]_clock_1 = GLOBAL(A1L5);
L1_q_b[7]_PORT_B_data_out = MEMORY(L1_q_b[7]_PORT_A_data_in_reg, L1_q_b[7]_PORT_B_data_in_reg, L1_q_b[7]_PORT_A_address_reg, L1_q_b[7]_PORT_B_address_reg, L1_q_b[7]_PORT_A_write_enable_reg, L1_q_b[7]_PORT_B_write_enable_reg, , , L1_q_b[7]_clock_0, L1_q_b[7]_clock_1, , , , );
L1_q_b[7] = L1_q_b[7]_PORT_B_data_out[0];

--L1_q_a[0] is sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[0] at M4K_X13_Y10
L1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
L1_q_a[7]_PORT_A_data_in_reg = DFFE(L1_q_a[7]_PORT_A_data_in, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_data_in = BUS(M1_ram_rom_data_reg[7], M1_ram_rom_data_reg[6], M1_ram_rom_data_reg[5], M1_ram_rom_data_reg[4], M1_ram_rom_data_reg[3], M1_ram_rom_data_reg[2], M1_ram_rom_data_reg[1], M1_ram_rom_data_reg[0]);
L1_q_a[7]_PORT_B_data_in_reg = DFFE(L1_q_a[7]_PORT_B_data_in, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_PORT_A_address = BUS(E1_sinout[0], E1_sinout[1], E1_sinout[2], E1_sinout[3], E1_sinout[4], E1_sinout[5], E1_sinout[6], E1_sinout[7], E1_sinout[8]);
L1_q_a[7]_PORT_A_address_reg = DFFE(L1_q_a[7]_PORT_A_address, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
L1_q_a[7]_PORT_B_address_reg = DFFE(L1_q_a[7]_PORT_B_address, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_PORT_A_write_enable = GND;
L1_q_a[7]_PORT_A_write_enable_reg = DFFE(L1_q_a[7]_PORT_A_write_enable, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_write_enable = M1L23;
L1_q_a[7]_PORT_B_write_enable_reg = DFFE(L1_q_a[7]_PORT_B_write_enable, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_clock_0 = GLOBAL(clk);
L1_q_a[7]_clock_1 = GLOBAL(A1L5);
L1_q_a[7]_PORT_A_data_out = MEMORY(L1_q_a[7]_PORT_A_data_in_reg, L1_q_a[7]_PORT_B_data_in_reg, L1_q_a[7]_PORT_A_address_reg, L1_q_a[7]_PORT_B_address_reg, L1_q_a[7]_PORT_A_write_enable_reg, L1_q_a[7]_PORT_B_write_enable_reg, , , L1_q_a[7]_clock_0, L1_q_a[7]_clock_1, , , , );
L1_q_a[7]_PORT_A_data_out_reg = DFFE(L1_q_a[7]_PORT_A_data_out, L1_q_a[7]_clock_0, , , );
L1_q_a[0] = L1_q_a[7]_PORT_A_data_out_reg[7];

--L1_q_a[1] is sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[1] at M4K_X13_Y10
L1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
L1_q_a[7]_PORT_A_data_in_reg = DFFE(L1_q_a[7]_PORT_A_data_in, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_data_in = BUS(M1_ram_rom_data_reg[7], M1_ram_rom_data_reg[6], M1_ram_rom_data_reg[5], M1_ram_rom_data_reg[4], M1_ram_rom_data_reg[3], M1_ram_rom_data_reg[2], M1_ram_rom_data_reg[1], M1_ram_rom_data_reg[0]);
L1_q_a[7]_PORT_B_data_in_reg = DFFE(L1_q_a[7]_PORT_B_data_in, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_PORT_A_address = BUS(E1_sinout[0], E1_sinout[1], E1_sinout[2], E1_sinout[3], E1_sinout[4], E1_sinout[5], E1_sinout[6], E1_sinout[7], E1_sinout[8]);
L1_q_a[7]_PORT_A_address_reg = DFFE(L1_q_a[7]_PORT_A_address, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
L1_q_a[7]_PORT_B_address_reg = DFFE(L1_q_a[7]_PORT_B_address, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_PORT_A_write_enable = GND;
L1_q_a[7]_PORT_A_write_enable_reg = DFFE(L1_q_a[7]_PORT_A_write_enable, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_write_enable = M1L23;
L1_q_a[7]_PORT_B_write_enable_reg = DFFE(L1_q_a[7]_PORT_B_write_enable, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_clock_0 = GLOBAL(clk);
L1_q_a[7]_clock_1 = GLOBAL(A1L5);
L1_q_a[7]_PORT_A_data_out = MEMORY(L1_q_a[7]_PORT_A_data_in_reg, L1_q_a[7]_PORT_B_data_in_reg, L1_q_a[7]_PORT_A_address_reg, L1_q_a[7]_PORT_B_address_reg, L1_q_a[7]_PORT_A_write_enable_reg, L1_q_a[7]_PORT_B_write_enable_reg, , , L1_q_a[7]_clock_0, L1_q_a[7]_clock_1, , , , );
L1_q_a[7]_PORT_A_data_out_reg = DFFE(L1_q_a[7]_PORT_A_data_out, L1_q_a[7]_clock_0, , , );
L1_q_a[1] = L1_q_a[7]_PORT_A_data_out_reg[6];

--L1_q_a[2] is sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[2] at M4K_X13_Y10
L1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
L1_q_a[7]_PORT_A_data_in_reg = DFFE(L1_q_a[7]_PORT_A_data_in, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_data_in = BUS(M1_ram_rom_data_reg[7], M1_ram_rom_data_reg[6], M1_ram_rom_data_reg[5], M1_ram_rom_data_reg[4], M1_ram_rom_data_reg[3], M1_ram_rom_data_reg[2], M1_ram_rom_data_reg[1], M1_ram_rom_data_reg[0]);
L1_q_a[7]_PORT_B_data_in_reg = DFFE(L1_q_a[7]_PORT_B_data_in, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_PORT_A_address = BUS(E1_sinout[0], E1_sinout[1], E1_sinout[2], E1_sinout[3], E1_sinout[4], E1_sinout[5], E1_sinout[6], E1_sinout[7], E1_sinout[8]);
L1_q_a[7]_PORT_A_address_reg = DFFE(L1_q_a[7]_PORT_A_address, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
L1_q_a[7]_PORT_B_address_reg = DFFE(L1_q_a[7]_PORT_B_address, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_PORT_A_write_enable = GND;
L1_q_a[7]_PORT_A_write_enable_reg = DFFE(L1_q_a[7]_PORT_A_write_enable, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_write_enable = M1L23;
L1_q_a[7]_PORT_B_write_enable_reg = DFFE(L1_q_a[7]_PORT_B_write_enable, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_clock_0 = GLOBAL(clk);
L1_q_a[7]_clock_1 = GLOBAL(A1L5);
L1_q_a[7]_PORT_A_data_out = MEMORY(L1_q_a[7]_PORT_A_data_in_reg, L1_q_a[7]_PORT_B_data_in_reg, L1_q_a[7]_PORT_A_address_reg, L1_q_a[7]_PORT_B_address_reg, L1_q_a[7]_PORT_A_write_enable_reg, L1_q_a[7]_PORT_B_write_enable_reg, , , L1_q_a[7]_clock_0, L1_q_a[7]_clock_1, , , , );
L1_q_a[7]_PORT_A_data_out_reg = DFFE(L1_q_a[7]_PORT_A_data_out, L1_q_a[7]_clock_0, , , );
L1_q_a[2] = L1_q_a[7]_PORT_A_data_out_reg[5];

--L1_q_a[3] is sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[3] at M4K_X13_Y10
L1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
L1_q_a[7]_PORT_A_data_in_reg = DFFE(L1_q_a[7]_PORT_A_data_in, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_data_in = BUS(M1_ram_rom_data_reg[7], M1_ram_rom_data_reg[6], M1_ram_rom_data_reg[5], M1_ram_rom_data_reg[4], M1_ram_rom_data_reg[3], M1_ram_rom_data_reg[2], M1_ram_rom_data_reg[1], M1_ram_rom_data_reg[0]);
L1_q_a[7]_PORT_B_data_in_reg = DFFE(L1_q_a[7]_PORT_B_data_in, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_PORT_A_address = BUS(E1_sinout[0], E1_sinout[1], E1_sinout[2], E1_sinout[3], E1_sinout[4], E1_sinout[5], E1_sinout[6], E1_sinout[7], E1_sinout[8]);
L1_q_a[7]_PORT_A_address_reg = DFFE(L1_q_a[7]_PORT_A_address, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
L1_q_a[7]_PORT_B_address_reg = DFFE(L1_q_a[7]_PORT_B_address, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_PORT_A_write_enable = GND;
L1_q_a[7]_PORT_A_write_enable_reg = DFFE(L1_q_a[7]_PORT_A_write_enable, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_write_enable = M1L23;
L1_q_a[7]_PORT_B_write_enable_reg = DFFE(L1_q_a[7]_PORT_B_write_enable, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_clock_0 = GLOBAL(clk);
L1_q_a[7]_clock_1 = GLOBAL(A1L5);
L1_q_a[7]_PORT_A_data_out = MEMORY(L1_q_a[7]_PORT_A_data_in_reg, L1_q_a[7]_PORT_B_data_in_reg, L1_q_a[7]_PORT_A_address_reg, L1_q_a[7]_PORT_B_address_reg, L1_q_a[7]_PORT_A_write_enable_reg, L1_q_a[7]_PORT_B_write_enable_reg, , , L1_q_a[7]_clock_0, L1_q_a[7]_clock_1, , , , );
L1_q_a[7]_PORT_A_data_out_reg = DFFE(L1_q_a[7]_PORT_A_data_out, L1_q_a[7]_clock_0, , , );
L1_q_a[3] = L1_q_a[7]_PORT_A_data_out_reg[4];

--L1_q_a[4] is sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[4] at M4K_X13_Y10
L1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
L1_q_a[7]_PORT_A_data_in_reg = DFFE(L1_q_a[7]_PORT_A_data_in, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_data_in = BUS(M1_ram_rom_data_reg[7], M1_ram_rom_data_reg[6], M1_ram_rom_data_reg[5], M1_ram_rom_data_reg[4], M1_ram_rom_data_reg[3], M1_ram_rom_data_reg[2], M1_ram_rom_data_reg[1], M1_ram_rom_data_reg[0]);
L1_q_a[7]_PORT_B_data_in_reg = DFFE(L1_q_a[7]_PORT_B_data_in, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_PORT_A_address = BUS(E1_sinout[0], E1_sinout[1], E1_sinout[2], E1_sinout[3], E1_sinout[4], E1_sinout[5], E1_sinout[6], E1_sinout[7], E1_sinout[8]);
L1_q_a[7]_PORT_A_address_reg = DFFE(L1_q_a[7]_PORT_A_address, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
L1_q_a[7]_PORT_B_address_reg = DFFE(L1_q_a[7]_PORT_B_address, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_PORT_A_write_enable = GND;
L1_q_a[7]_PORT_A_write_enable_reg = DFFE(L1_q_a[7]_PORT_A_write_enable, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_write_enable = M1L23;
L1_q_a[7]_PORT_B_write_enable_reg = DFFE(L1_q_a[7]_PORT_B_write_enable, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_clock_0 = GLOBAL(clk);
L1_q_a[7]_clock_1 = GLOBAL(A1L5);
L1_q_a[7]_PORT_A_data_out = MEMORY(L1_q_a[7]_PORT_A_data_in_reg, L1_q_a[7]_PORT_B_data_in_reg, L1_q_a[7]_PORT_A_address_reg, L1_q_a[7]_PORT_B_address_reg, L1_q_a[7]_PORT_A_write_enable_reg, L1_q_a[7]_PORT_B_write_enable_reg, , , L1_q_a[7]_clock_0, L1_q_a[7]_clock_1, , , , );
L1_q_a[7]_PORT_A_data_out_reg = DFFE(L1_q_a[7]_PORT_A_data_out, L1_q_a[7]_clock_0, , , );
L1_q_a[4] = L1_q_a[7]_PORT_A_data_out_reg[3];

--L1_q_a[5] is sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[5] at M4K_X13_Y10
L1_q_a[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
L1_q_a[7]_PORT_A_data_in_reg = DFFE(L1_q_a[7]_PORT_A_data_in, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_data_in = BUS(M1_ram_rom_data_reg[7], M1_ram_rom_data_reg[6], M1_ram_rom_data_reg[5], M1_ram_rom_data_reg[4], M1_ram_rom_data_reg[3], M1_ram_rom_data_reg[2], M1_ram_rom_data_reg[1], M1_ram_rom_data_reg[0]);
L1_q_a[7]_PORT_B_data_in_reg = DFFE(L1_q_a[7]_PORT_B_data_in, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_PORT_A_address = BUS(E1_sinout[0], E1_sinout[1], E1_sinout[2], E1_sinout[3], E1_sinout[4], E1_sinout[5], E1_sinout[6], E1_sinout[7], E1_sinout[8]);
L1_q_a[7]_PORT_A_address_reg = DFFE(L1_q_a[7]_PORT_A_address, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_address = BUS(P1_safe_q[0], P1_safe_q[1], P1_safe_q[2], P1_safe_q[3], P1_safe_q[4], P1_safe_q[5], P1_safe_q[6], P1_safe_q[7], P1_safe_q[8]);
L1_q_a[7]_PORT_B_address_reg = DFFE(L1_q_a[7]_PORT_B_address, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_PORT_A_write_enable = GND;
L1_q_a[7]_PORT_A_write_enable_reg = DFFE(L1_q_a[7]_PORT_A_write_enable, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_PORT_B_write_enable = M1L23;
L1_q_a[7]_PORT_B_write_enable_reg = DFFE(L1_q_a[7]_PORT_B_write_enable, L1_q_a[7]_clock_1, , , );
L1_q_a[7]_clock_0 = GLOBAL(clk);
L1_q_a[7]_clock_1 = GLOBAL(A1L5);
L1_q_a[7]_PORT_A_data_out = MEMORY(L1_q_a[7]_PORT_A_data_in_reg, L1_q_a[7]_PORT_B_data_in_reg, L1_q_a[7]_PORT_A_address_reg, L1_q_a[7]_PORT_B_address_reg, L1_q_a[7]_PORT_A_write_enable_reg, L1_q_a[7]_PORT_B_write_enable_reg, , , L1_q_a[7]_clock_0, L1_q_a[7]_clock_1, , , , );
L1_q_a[7]_PORT_A_data_out_reg = DFFE(L1_q_a[7]_PORT_A_data_out, L1_q_a[7]_clock_0, , , );
L1_q_a[5] = L1_q_a[7]_PORT_A_data_out_reg[2];