piso.map.eqn

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

--L2_q_a[1] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
L2_q_a[1]_PORT_A_data_in = VCC;
L2_q_a[1]_PORT_A_data_in_reg = DFFE(L2_q_a[1]_PORT_A_data_in, L2_q_a[1]_clock_0, , , );
L2_q_a[1]_PORT_B_data_in = M2_ram_rom_data_reg[1];
L2_q_a[1]_PORT_B_data_in_reg = DFFE(L2_q_a[1]_PORT_B_data_in, L2_q_a[1]_clock_1, , , );
L2_q_a[1]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_a[1]_PORT_A_address_reg = DFFE(L2_q_a[1]_PORT_A_address, L2_q_a[1]_clock_0, , , );
L2_q_a[1]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_a[1]_PORT_B_address_reg = DFFE(L2_q_a[1]_PORT_B_address, L2_q_a[1]_clock_1, , , );
L2_q_a[1]_PORT_A_write_enable = GND;
L2_q_a[1]_PORT_A_write_enable_reg = DFFE(L2_q_a[1]_PORT_A_write_enable, L2_q_a[1]_clock_0, , , );
L2_q_a[1]_PORT_B_write_enable = M2L23;
L2_q_a[1]_PORT_B_write_enable_reg = DFFE(L2_q_a[1]_PORT_B_write_enable, L2_q_a[1]_clock_1, , , );
L2_q_a[1]_clock_0 = clk;
L2_q_a[1]_clock_1 = A1L5;
L2_q_a[1]_PORT_A_data_out = MEMORY(L2_q_a[1]_PORT_A_data_in_reg, L2_q_a[1]_PORT_B_data_in_reg, L2_q_a[1]_PORT_A_address_reg, L2_q_a[1]_PORT_B_address_reg, L2_q_a[1]_PORT_A_write_enable_reg, L2_q_a[1]_PORT_B_write_enable_reg, , , L2_q_a[1]_clock_0, L2_q_a[1]_clock_1, , , , );
L2_q_a[1]_PORT_A_data_out_reg = DFFE(L2_q_a[1]_PORT_A_data_out, L2_q_a[1]_clock_0, , , );
L2_q_a[1] = L2_q_a[1]_PORT_A_data_out_reg[0];

--L2_q_b[1] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_b[1]
L2_q_b[1]_PORT_A_data_in = VCC;
L2_q_b[1]_PORT_A_data_in_reg = DFFE(L2_q_b[1]_PORT_A_data_in, L2_q_b[1]_clock_0, , , );
L2_q_b[1]_PORT_B_data_in = M2_ram_rom_data_reg[1];
L2_q_b[1]_PORT_B_data_in_reg = DFFE(L2_q_b[1]_PORT_B_data_in, L2_q_b[1]_clock_1, , , );
L2_q_b[1]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_b[1]_PORT_A_address_reg = DFFE(L2_q_b[1]_PORT_A_address, L2_q_b[1]_clock_0, , , );
L2_q_b[1]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_b[1]_PORT_B_address_reg = DFFE(L2_q_b[1]_PORT_B_address, L2_q_b[1]_clock_1, , , );
L2_q_b[1]_PORT_A_write_enable = GND;
L2_q_b[1]_PORT_A_write_enable_reg = DFFE(L2_q_b[1]_PORT_A_write_enable, L2_q_b[1]_clock_0, , , );
L2_q_b[1]_PORT_B_write_enable = M2L23;
L2_q_b[1]_PORT_B_write_enable_reg = DFFE(L2_q_b[1]_PORT_B_write_enable, L2_q_b[1]_clock_1, , , );
L2_q_b[1]_clock_0 = clk;
L2_q_b[1]_clock_1 = A1L5;
L2_q_b[1]_PORT_B_data_out = MEMORY(L2_q_b[1]_PORT_A_data_in_reg, L2_q_b[1]_PORT_B_data_in_reg, L2_q_b[1]_PORT_A_address_reg, L2_q_b[1]_PORT_B_address_reg, L2_q_b[1]_PORT_A_write_enable_reg, L2_q_b[1]_PORT_B_write_enable_reg, , , L2_q_b[1]_clock_0, L2_q_b[1]_clock_1, , , , );
L2_q_b[1] = L2_q_b[1]_PORT_B_data_out[0];


--L2_q_a[0] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
L2_q_a[0]_PORT_A_data_in = VCC;
L2_q_a[0]_PORT_A_data_in_reg = DFFE(L2_q_a[0]_PORT_A_data_in, L2_q_a[0]_clock_0, , , );
L2_q_a[0]_PORT_B_data_in = M2_ram_rom_data_reg[0];
L2_q_a[0]_PORT_B_data_in_reg = DFFE(L2_q_a[0]_PORT_B_data_in, L2_q_a[0]_clock_1, , , );
L2_q_a[0]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_a[0]_PORT_A_address_reg = DFFE(L2_q_a[0]_PORT_A_address, L2_q_a[0]_clock_0, , , );
L2_q_a[0]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_a[0]_PORT_B_address_reg = DFFE(L2_q_a[0]_PORT_B_address, L2_q_a[0]_clock_1, , , );
L2_q_a[0]_PORT_A_write_enable = GND;
L2_q_a[0]_PORT_A_write_enable_reg = DFFE(L2_q_a[0]_PORT_A_write_enable, L2_q_a[0]_clock_0, , , );
L2_q_a[0]_PORT_B_write_enable = M2L23;
L2_q_a[0]_PORT_B_write_enable_reg = DFFE(L2_q_a[0]_PORT_B_write_enable, L2_q_a[0]_clock_1, , , );
L2_q_a[0]_clock_0 = clk;
L2_q_a[0]_clock_1 = A1L5;
L2_q_a[0]_PORT_A_data_out = MEMORY(L2_q_a[0]_PORT_A_data_in_reg, L2_q_a[0]_PORT_B_data_in_reg, L2_q_a[0]_PORT_A_address_reg, L2_q_a[0]_PORT_B_address_reg, L2_q_a[0]_PORT_A_write_enable_reg, L2_q_a[0]_PORT_B_write_enable_reg, , , L2_q_a[0]_clock_0, L2_q_a[0]_clock_1, , , , );
L2_q_a[0]_PORT_A_data_out_reg = DFFE(L2_q_a[0]_PORT_A_data_out, L2_q_a[0]_clock_0, , , );
L2_q_a[0] = L2_q_a[0]_PORT_A_data_out_reg[0];

--L2_q_b[0] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_b[0]
L2_q_b[0]_PORT_A_data_in = VCC;
L2_q_b[0]_PORT_A_data_in_reg = DFFE(L2_q_b[0]_PORT_A_data_in, L2_q_b[0]_clock_0, , , );
L2_q_b[0]_PORT_B_data_in = M2_ram_rom_data_reg[0];
L2_q_b[0]_PORT_B_data_in_reg = DFFE(L2_q_b[0]_PORT_B_data_in, L2_q_b[0]_clock_1, , , );
L2_q_b[0]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_b[0]_PORT_A_address_reg = DFFE(L2_q_b[0]_PORT_A_address, L2_q_b[0]_clock_0, , , );
L2_q_b[0]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_b[0]_PORT_B_address_reg = DFFE(L2_q_b[0]_PORT_B_address, L2_q_b[0]_clock_1, , , );
L2_q_b[0]_PORT_A_write_enable = GND;
L2_q_b[0]_PORT_A_write_enable_reg = DFFE(L2_q_b[0]_PORT_A_write_enable, L2_q_b[0]_clock_0, , , );
L2_q_b[0]_PORT_B_write_enable = M2L23;
L2_q_b[0]_PORT_B_write_enable_reg = DFFE(L2_q_b[0]_PORT_B_write_enable, L2_q_b[0]_clock_1, , , );
L2_q_b[0]_clock_0 = clk;
L2_q_b[0]_clock_1 = A1L5;
L2_q_b[0]_PORT_B_data_out = MEMORY(L2_q_b[0]_PORT_A_data_in_reg, L2_q_b[0]_PORT_B_data_in_reg, L2_q_b[0]_PORT_A_address_reg, L2_q_b[0]_PORT_B_address_reg, L2_q_b[0]_PORT_A_write_enable_reg, L2_q_b[0]_PORT_B_write_enable_reg, , , L2_q_b[0]_clock_0, L2_q_b[0]_clock_1, , , , );
L2_q_b[0] = L2_q_b[0]_PORT_B_data_out[0];


--A1L6 is altera_internal_jtag~TDO
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !F1L32Q);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !F1L32Q);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !F1L32Q);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !F1L32Q);


--B1_\P1:cnt[15] is pf:s1|\P1:cnt[15]
--operation mode is normal

B1_\P1:cnt[15]_lut_out = B1_b[15];
B1_\P1:cnt[15] = DFFEA(B1_\P1:cnt[15]_lut_out, clk, VCC, , B1L93, , );


--B1_\P1:cnt[14] is pf:s1|\P1:cnt[14]
--operation mode is normal

B1_\P1:cnt[14]_lut_out = B1_b[14];
B1_\P1:cnt[14] = DFFEA(B1_\P1:cnt[14]_lut_out, clk, VCC, , B1L93, , );


--B1_\P1:cnt[13] is pf:s1|\P1:cnt[13]
--operation mode is normal

B1_\P1:cnt[13]_lut_out = B1_b[13];
B1_\P1:cnt[13] = DFFEA(B1_\P1:cnt[13]_lut_out, clk, VCC, , B1L93, , );


--B1_\P1:cnt[12] is pf:s1|\P1:cnt[12]
--operation mode is normal

B1_\P1:cnt[12]_lut_out = B1_b[12];
B1_\P1:cnt[12] = DFFEA(B1_\P1:cnt[12]_lut_out, clk, VCC, , B1L93, , );


--B1L53 is pf:s1|reduce_nor~124
--operation mode is normal

B1L53 = !B1_\P1:cnt[12] # !B1_\P1:cnt[13] # !B1_\P1:cnt[14] # !B1_\P1:cnt[15];


--B1_\P1:cnt[11] is pf:s1|\P1:cnt[11]
--operation mode is normal

B1_\P1:cnt[11]_lut_out = B1_b[11];
B1_\P1:cnt[11] = DFFEA(B1_\P1:cnt[11]_lut_out, clk, VCC, , B1L93, , );


--B1_\P1:cnt[10] is pf:s1|\P1:cnt[10]
--operation mode is normal

B1_\P1:cnt[10]_lut_out = B1_b[10];
B1_\P1:cnt[10] = DFFEA(B1_\P1:cnt[10]_lut_out, clk, VCC, , B1L93, , );


--B1_\P1:cnt[9] is pf:s1|\P1:cnt[9]
--operation mode is normal

B1_\P1:cnt[9]_lut_out = B1_b[9];
B1_\P1:cnt[9] = DFFEA(B1_\P1:cnt[9]_lut_out, clk, VCC, , B1L93, , );


--B1_\P1:cnt[8] is pf:s1|\P1:cnt[8]
--operation mode is normal

B1_\P1:cnt[8]_lut_out = B1_b[8];
B1_\P1:cnt[8] = DFFEA(B1_\P1:cnt[8]_lut_out, clk, VCC, , B1L93, , );


--B1L63 is pf:s1|reduce_nor~125
--operation mode is normal

B1L63 = !B1_\P1:cnt[8] # !B1_\P1:cnt[9] # !B1_\P1:cnt[10] # !B1_\P1:cnt[11];


--B1_\P1:cnt[7] is pf:s1|\P1:cnt[7]
--operation mode is normal

B1_\P1:cnt[7]_lut_out = B1_b[7];
B1_\P1:cnt[7] = DFFEA(B1_\P1:cnt[7]_lut_out, clk, VCC, , B1L93, , );


--B1_\P1:cnt[6] is pf:s1|\P1:cnt[6]
--operation mode is normal

B1_\P1:cnt[6]_lut_out = B1_b[6];
B1_\P1:cnt[6] = DFFEA(B1_\P1:cnt[6]_lut_out, clk, VCC, , B1L93, , );


--B1_\P1:cnt[5] is pf:s1|\P1:cnt[5]
--operation mode is normal

B1_\P1:cnt[5]_lut_out = B1_b[5];
B1_\P1:cnt[5] = DFFEA(B1_\P1:cnt[5]_lut_out, clk, VCC, , B1L93, , );


--B1_\P1:cnt[4] is pf:s1|\P1:cnt[4]
--operation mode is normal

B1_\P1:cnt[4]_lut_out = B1_b[4];
B1_\P1:cnt[4] = DFFEA(B1_\P1:cnt[4]_lut_out, clk, VCC, , B1L93, , );


--B1L73 is pf:s1|reduce_nor~126
--operation mode is normal

B1L73 = !B1_\P1:cnt[4] # !B1_\P1:cnt[5] # !B1_\P1:cnt[6] # !B1_\P1:cnt[7];