piso.map.eqn

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

L2_q_a[6]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_a[6]_PORT_B_address_reg = DFFE(L2_q_a[6]_PORT_B_address, L2_q_a[6]_clock_1, , , );
L2_q_a[6]_PORT_A_write_enable = GND;
L2_q_a[6]_PORT_A_write_enable_reg = DFFE(L2_q_a[6]_PORT_A_write_enable, L2_q_a[6]_clock_0, , , );
L2_q_a[6]_PORT_B_write_enable = M2L23;
L2_q_a[6]_PORT_B_write_enable_reg = DFFE(L2_q_a[6]_PORT_B_write_enable, L2_q_a[6]_clock_1, , , );
L2_q_a[6]_clock_0 = clk;
L2_q_a[6]_clock_1 = A1L5;
L2_q_a[6]_PORT_A_data_out = MEMORY(L2_q_a[6]_PORT_A_data_in_reg, L2_q_a[6]_PORT_B_data_in_reg, L2_q_a[6]_PORT_A_address_reg, L2_q_a[6]_PORT_B_address_reg, L2_q_a[6]_PORT_A_write_enable_reg, L2_q_a[6]_PORT_B_write_enable_reg, , , L2_q_a[6]_clock_0, L2_q_a[6]_clock_1, , , , );
L2_q_a[6]_PORT_A_data_out_reg = DFFE(L2_q_a[6]_PORT_A_data_out, L2_q_a[6]_clock_0, , , );
L2_q_a[6] = L2_q_a[6]_PORT_A_data_out_reg[0];

--L2_q_b[6] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_b[6]
L2_q_b[6]_PORT_A_data_in = VCC;
L2_q_b[6]_PORT_A_data_in_reg = DFFE(L2_q_b[6]_PORT_A_data_in, L2_q_b[6]_clock_0, , , );
L2_q_b[6]_PORT_B_data_in = M2_ram_rom_data_reg[6];
L2_q_b[6]_PORT_B_data_in_reg = DFFE(L2_q_b[6]_PORT_B_data_in, L2_q_b[6]_clock_1, , , );
L2_q_b[6]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_b[6]_PORT_A_address_reg = DFFE(L2_q_b[6]_PORT_A_address, L2_q_b[6]_clock_0, , , );
L2_q_b[6]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_b[6]_PORT_B_address_reg = DFFE(L2_q_b[6]_PORT_B_address, L2_q_b[6]_clock_1, , , );
L2_q_b[6]_PORT_A_write_enable = GND;
L2_q_b[6]_PORT_A_write_enable_reg = DFFE(L2_q_b[6]_PORT_A_write_enable, L2_q_b[6]_clock_0, , , );
L2_q_b[6]_PORT_B_write_enable = M2L23;
L2_q_b[6]_PORT_B_write_enable_reg = DFFE(L2_q_b[6]_PORT_B_write_enable, L2_q_b[6]_clock_1, , , );
L2_q_b[6]_clock_0 = clk;
L2_q_b[6]_clock_1 = A1L5;
L2_q_b[6]_PORT_B_data_out = MEMORY(L2_q_b[6]_PORT_A_data_in_reg, L2_q_b[6]_PORT_B_data_in_reg, L2_q_b[6]_PORT_A_address_reg, L2_q_b[6]_PORT_B_address_reg, L2_q_b[6]_PORT_A_write_enable_reg, L2_q_b[6]_PORT_B_write_enable_reg, , , L2_q_b[6]_clock_0, L2_q_b[6]_clock_1, , , , );
L2_q_b[6] = L2_q_b[6]_PORT_B_data_out[0];


--L2_q_a[5] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
L2_q_a[5]_PORT_A_data_in = VCC;
L2_q_a[5]_PORT_A_data_in_reg = DFFE(L2_q_a[5]_PORT_A_data_in, L2_q_a[5]_clock_0, , , );
L2_q_a[5]_PORT_B_data_in = M2_ram_rom_data_reg[5];
L2_q_a[5]_PORT_B_data_in_reg = DFFE(L2_q_a[5]_PORT_B_data_in, L2_q_a[5]_clock_1, , , );
L2_q_a[5]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_a[5]_PORT_A_address_reg = DFFE(L2_q_a[5]_PORT_A_address, L2_q_a[5]_clock_0, , , );
L2_q_a[5]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_a[5]_PORT_B_address_reg = DFFE(L2_q_a[5]_PORT_B_address, L2_q_a[5]_clock_1, , , );
L2_q_a[5]_PORT_A_write_enable = GND;
L2_q_a[5]_PORT_A_write_enable_reg = DFFE(L2_q_a[5]_PORT_A_write_enable, L2_q_a[5]_clock_0, , , );
L2_q_a[5]_PORT_B_write_enable = M2L23;
L2_q_a[5]_PORT_B_write_enable_reg = DFFE(L2_q_a[5]_PORT_B_write_enable, L2_q_a[5]_clock_1, , , );
L2_q_a[5]_clock_0 = clk;
L2_q_a[5]_clock_1 = A1L5;
L2_q_a[5]_PORT_A_data_out = MEMORY(L2_q_a[5]_PORT_A_data_in_reg, L2_q_a[5]_PORT_B_data_in_reg, L2_q_a[5]_PORT_A_address_reg, L2_q_a[5]_PORT_B_address_reg, L2_q_a[5]_PORT_A_write_enable_reg, L2_q_a[5]_PORT_B_write_enable_reg, , , L2_q_a[5]_clock_0, L2_q_a[5]_clock_1, , , , );
L2_q_a[5]_PORT_A_data_out_reg = DFFE(L2_q_a[5]_PORT_A_data_out, L2_q_a[5]_clock_0, , , );
L2_q_a[5] = L2_q_a[5]_PORT_A_data_out_reg[0];

--L2_q_b[5] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_b[5]
L2_q_b[5]_PORT_A_data_in = VCC;
L2_q_b[5]_PORT_A_data_in_reg = DFFE(L2_q_b[5]_PORT_A_data_in, L2_q_b[5]_clock_0, , , );
L2_q_b[5]_PORT_B_data_in = M2_ram_rom_data_reg[5];
L2_q_b[5]_PORT_B_data_in_reg = DFFE(L2_q_b[5]_PORT_B_data_in, L2_q_b[5]_clock_1, , , );
L2_q_b[5]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_b[5]_PORT_A_address_reg = DFFE(L2_q_b[5]_PORT_A_address, L2_q_b[5]_clock_0, , , );
L2_q_b[5]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_b[5]_PORT_B_address_reg = DFFE(L2_q_b[5]_PORT_B_address, L2_q_b[5]_clock_1, , , );
L2_q_b[5]_PORT_A_write_enable = GND;
L2_q_b[5]_PORT_A_write_enable_reg = DFFE(L2_q_b[5]_PORT_A_write_enable, L2_q_b[5]_clock_0, , , );
L2_q_b[5]_PORT_B_write_enable = M2L23;
L2_q_b[5]_PORT_B_write_enable_reg = DFFE(L2_q_b[5]_PORT_B_write_enable, L2_q_b[5]_clock_1, , , );
L2_q_b[5]_clock_0 = clk;
L2_q_b[5]_clock_1 = A1L5;
L2_q_b[5]_PORT_B_data_out = MEMORY(L2_q_b[5]_PORT_A_data_in_reg, L2_q_b[5]_PORT_B_data_in_reg, L2_q_b[5]_PORT_A_address_reg, L2_q_b[5]_PORT_B_address_reg, L2_q_b[5]_PORT_A_write_enable_reg, L2_q_b[5]_PORT_B_write_enable_reg, , , L2_q_b[5]_clock_0, L2_q_b[5]_clock_1, , , , );
L2_q_b[5] = L2_q_b[5]_PORT_B_data_out[0];


--L2_q_a[4] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
L2_q_a[4]_PORT_A_data_in = VCC;
L2_q_a[4]_PORT_A_data_in_reg = DFFE(L2_q_a[4]_PORT_A_data_in, L2_q_a[4]_clock_0, , , );
L2_q_a[4]_PORT_B_data_in = M2_ram_rom_data_reg[4];
L2_q_a[4]_PORT_B_data_in_reg = DFFE(L2_q_a[4]_PORT_B_data_in, L2_q_a[4]_clock_1, , , );
L2_q_a[4]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_a[4]_PORT_A_address_reg = DFFE(L2_q_a[4]_PORT_A_address, L2_q_a[4]_clock_0, , , );
L2_q_a[4]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_a[4]_PORT_B_address_reg = DFFE(L2_q_a[4]_PORT_B_address, L2_q_a[4]_clock_1, , , );
L2_q_a[4]_PORT_A_write_enable = GND;
L2_q_a[4]_PORT_A_write_enable_reg = DFFE(L2_q_a[4]_PORT_A_write_enable, L2_q_a[4]_clock_0, , , );
L2_q_a[4]_PORT_B_write_enable = M2L23;
L2_q_a[4]_PORT_B_write_enable_reg = DFFE(L2_q_a[4]_PORT_B_write_enable, L2_q_a[4]_clock_1, , , );
L2_q_a[4]_clock_0 = clk;
L2_q_a[4]_clock_1 = A1L5;
L2_q_a[4]_PORT_A_data_out = MEMORY(L2_q_a[4]_PORT_A_data_in_reg, L2_q_a[4]_PORT_B_data_in_reg, L2_q_a[4]_PORT_A_address_reg, L2_q_a[4]_PORT_B_address_reg, L2_q_a[4]_PORT_A_write_enable_reg, L2_q_a[4]_PORT_B_write_enable_reg, , , L2_q_a[4]_clock_0, L2_q_a[4]_clock_1, , , , );
L2_q_a[4]_PORT_A_data_out_reg = DFFE(L2_q_a[4]_PORT_A_data_out, L2_q_a[4]_clock_0, , , );
L2_q_a[4] = L2_q_a[4]_PORT_A_data_out_reg[0];

--L2_q_b[4] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_b[4]
L2_q_b[4]_PORT_A_data_in = VCC;
L2_q_b[4]_PORT_A_data_in_reg = DFFE(L2_q_b[4]_PORT_A_data_in, L2_q_b[4]_clock_0, , , );
L2_q_b[4]_PORT_B_data_in = M2_ram_rom_data_reg[4];
L2_q_b[4]_PORT_B_data_in_reg = DFFE(L2_q_b[4]_PORT_B_data_in, L2_q_b[4]_clock_1, , , );
L2_q_b[4]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_b[4]_PORT_A_address_reg = DFFE(L2_q_b[4]_PORT_A_address, L2_q_b[4]_clock_0, , , );
L2_q_b[4]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_b[4]_PORT_B_address_reg = DFFE(L2_q_b[4]_PORT_B_address, L2_q_b[4]_clock_1, , , );
L2_q_b[4]_PORT_A_write_enable = GND;
L2_q_b[4]_PORT_A_write_enable_reg = DFFE(L2_q_b[4]_PORT_A_write_enable, L2_q_b[4]_clock_0, , , );
L2_q_b[4]_PORT_B_write_enable = M2L23;
L2_q_b[4]_PORT_B_write_enable_reg = DFFE(L2_q_b[4]_PORT_B_write_enable, L2_q_b[4]_clock_1, , , );
L2_q_b[4]_clock_0 = clk;
L2_q_b[4]_clock_1 = A1L5;
L2_q_b[4]_PORT_B_data_out = MEMORY(L2_q_b[4]_PORT_A_data_in_reg, L2_q_b[4]_PORT_B_data_in_reg, L2_q_b[4]_PORT_A_address_reg, L2_q_b[4]_PORT_B_address_reg, L2_q_b[4]_PORT_A_write_enable_reg, L2_q_b[4]_PORT_B_write_enable_reg, , , L2_q_b[4]_clock_0, L2_q_b[4]_clock_1, , , , );
L2_q_b[4] = L2_q_b[4]_PORT_B_data_out[0];


--L2_q_a[3] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
L2_q_a[3]_PORT_A_data_in = VCC;
L2_q_a[3]_PORT_A_data_in_reg = DFFE(L2_q_a[3]_PORT_A_data_in, L2_q_a[3]_clock_0, , , );
L2_q_a[3]_PORT_B_data_in = M2_ram_rom_data_reg[3];
L2_q_a[3]_PORT_B_data_in_reg = DFFE(L2_q_a[3]_PORT_B_data_in, L2_q_a[3]_clock_1, , , );
L2_q_a[3]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_a[3]_PORT_A_address_reg = DFFE(L2_q_a[3]_PORT_A_address, L2_q_a[3]_clock_0, , , );
L2_q_a[3]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_a[3]_PORT_B_address_reg = DFFE(L2_q_a[3]_PORT_B_address, L2_q_a[3]_clock_1, , , );
L2_q_a[3]_PORT_A_write_enable = GND;
L2_q_a[3]_PORT_A_write_enable_reg = DFFE(L2_q_a[3]_PORT_A_write_enable, L2_q_a[3]_clock_0, , , );
L2_q_a[3]_PORT_B_write_enable = M2L23;
L2_q_a[3]_PORT_B_write_enable_reg = DFFE(L2_q_a[3]_PORT_B_write_enable, L2_q_a[3]_clock_1, , , );
L2_q_a[3]_clock_0 = clk;
L2_q_a[3]_clock_1 = A1L5;
L2_q_a[3]_PORT_A_data_out = MEMORY(L2_q_a[3]_PORT_A_data_in_reg, L2_q_a[3]_PORT_B_data_in_reg, L2_q_a[3]_PORT_A_address_reg, L2_q_a[3]_PORT_B_address_reg, L2_q_a[3]_PORT_A_write_enable_reg, L2_q_a[3]_PORT_B_write_enable_reg, , , L2_q_a[3]_clock_0, L2_q_a[3]_clock_1, , , , );
L2_q_a[3]_PORT_A_data_out_reg = DFFE(L2_q_a[3]_PORT_A_data_out, L2_q_a[3]_clock_0, , , );
L2_q_a[3] = L2_q_a[3]_PORT_A_data_out_reg[0];

--L2_q_b[3] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_b[3]
L2_q_b[3]_PORT_A_data_in = VCC;
L2_q_b[3]_PORT_A_data_in_reg = DFFE(L2_q_b[3]_PORT_A_data_in, L2_q_b[3]_clock_0, , , );
L2_q_b[3]_PORT_B_data_in = M2_ram_rom_data_reg[3];
L2_q_b[3]_PORT_B_data_in_reg = DFFE(L2_q_b[3]_PORT_B_data_in, L2_q_b[3]_clock_1, , , );
L2_q_b[3]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_b[3]_PORT_A_address_reg = DFFE(L2_q_b[3]_PORT_A_address, L2_q_b[3]_clock_0, , , );
L2_q_b[3]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_b[3]_PORT_B_address_reg = DFFE(L2_q_b[3]_PORT_B_address, L2_q_b[3]_clock_1, , , );
L2_q_b[3]_PORT_A_write_enable = GND;
L2_q_b[3]_PORT_A_write_enable_reg = DFFE(L2_q_b[3]_PORT_A_write_enable, L2_q_b[3]_clock_0, , , );
L2_q_b[3]_PORT_B_write_enable = M2L23;
L2_q_b[3]_PORT_B_write_enable_reg = DFFE(L2_q_b[3]_PORT_B_write_enable, L2_q_b[3]_clock_1, , , );
L2_q_b[3]_clock_0 = clk;
L2_q_b[3]_clock_1 = A1L5;
L2_q_b[3]_PORT_B_data_out = MEMORY(L2_q_b[3]_PORT_A_data_in_reg, L2_q_b[3]_PORT_B_data_in_reg, L2_q_b[3]_PORT_A_address_reg, L2_q_b[3]_PORT_B_address_reg, L2_q_b[3]_PORT_A_write_enable_reg, L2_q_b[3]_PORT_B_write_enable_reg, , , L2_q_b[3]_clock_0, L2_q_b[3]_clock_1, , , , );
L2_q_b[3] = L2_q_b[3]_PORT_B_data_out[0];


--L2_q_a[2] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 8, Port B Logical Depth: 512, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
L2_q_a[2]_PORT_A_data_in = VCC;
L2_q_a[2]_PORT_A_data_in_reg = DFFE(L2_q_a[2]_PORT_A_data_in, L2_q_a[2]_clock_0, , , );
L2_q_a[2]_PORT_B_data_in = M2_ram_rom_data_reg[2];
L2_q_a[2]_PORT_B_data_in_reg = DFFE(L2_q_a[2]_PORT_B_data_in, L2_q_a[2]_clock_1, , , );
L2_q_a[2]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_a[2]_PORT_A_address_reg = DFFE(L2_q_a[2]_PORT_A_address, L2_q_a[2]_clock_0, , , );
L2_q_a[2]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_a[2]_PORT_B_address_reg = DFFE(L2_q_a[2]_PORT_B_address, L2_q_a[2]_clock_1, , , );
L2_q_a[2]_PORT_A_write_enable = GND;
L2_q_a[2]_PORT_A_write_enable_reg = DFFE(L2_q_a[2]_PORT_A_write_enable, L2_q_a[2]_clock_0, , , );
L2_q_a[2]_PORT_B_write_enable = M2L23;
L2_q_a[2]_PORT_B_write_enable_reg = DFFE(L2_q_a[2]_PORT_B_write_enable, L2_q_a[2]_clock_1, , , );
L2_q_a[2]_clock_0 = clk;
L2_q_a[2]_clock_1 = A1L5;
L2_q_a[2]_PORT_A_data_out = MEMORY(L2_q_a[2]_PORT_A_data_in_reg, L2_q_a[2]_PORT_B_data_in_reg, L2_q_a[2]_PORT_A_address_reg, L2_q_a[2]_PORT_B_address_reg, L2_q_a[2]_PORT_A_write_enable_reg, L2_q_a[2]_PORT_B_write_enable_reg, , , L2_q_a[2]_clock_0, L2_q_a[2]_clock_1, , , , );
L2_q_a[2]_PORT_A_data_out_reg = DFFE(L2_q_a[2]_PORT_A_data_out, L2_q_a[2]_clock_0, , , );
L2_q_a[2] = L2_q_a[2]_PORT_A_data_out_reg[0];

--L2_q_b[2] is sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_b[2]
L2_q_b[2]_PORT_A_data_in = VCC;
L2_q_b[2]_PORT_A_data_in_reg = DFFE(L2_q_b[2]_PORT_A_data_in, L2_q_b[2]_clock_0, , , );
L2_q_b[2]_PORT_B_data_in = M2_ram_rom_data_reg[2];
L2_q_b[2]_PORT_B_data_in_reg = DFFE(L2_q_b[2]_PORT_B_data_in, L2_q_b[2]_clock_1, , , );
L2_q_b[2]_PORT_A_address = BUS(E1_stand[0], E1_stand[1], E1_stand[2], E1_stand[3], E1_stand[4], E1_stand[5], E1_stand[6], E1_stand[7], E1_stand[8]);
L2_q_b[2]_PORT_A_address_reg = DFFE(L2_q_b[2]_PORT_A_address, L2_q_b[2]_clock_0, , , );
L2_q_b[2]_PORT_B_address = BUS(P2_safe_q[0], P2_safe_q[1], P2_safe_q[2], P2_safe_q[3], P2_safe_q[4], P2_safe_q[5], P2_safe_q[6], P2_safe_q[7], P2_safe_q[8]);
L2_q_b[2]_PORT_B_address_reg = DFFE(L2_q_b[2]_PORT_B_address, L2_q_b[2]_clock_1, , , );
L2_q_b[2]_PORT_A_write_enable = GND;
L2_q_b[2]_PORT_A_write_enable_reg = DFFE(L2_q_b[2]_PORT_A_write_enable, L2_q_b[2]_clock_0, , , );
L2_q_b[2]_PORT_B_write_enable = M2L23;
L2_q_b[2]_PORT_B_write_enable_reg = DFFE(L2_q_b[2]_PORT_B_write_enable, L2_q_b[2]_clock_1, , , );
L2_q_b[2]_clock_0 = clk;
L2_q_b[2]_clock_1 = A1L5;
L2_q_b[2]_PORT_B_data_out = MEMORY(L2_q_b[2]_PORT_A_data_in_reg, L2_q_b[2]_PORT_B_data_in_reg, L2_q_b[2]_PORT_A_address_reg, L2_q_b[2]_PORT_B_address_reg, L2_q_b[2]_PORT_A_write_enable_reg, L2_q_b[2]_PORT_B_write_enable_reg, , , L2_q_b[2]_clock_0, L2_q_b[2]_clock_1, , , , );
L2_q_b[2] = L2_q_b[2]_PORT_B_data_out[0];