piso.tan.rpt

FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl

; Timing Analyzer Settings                                                               ;
+-------------------------------------------------------+--------------------+------+----+
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1C3T144C8        ;      ;    ;
; Timing Models                                         ; Production         ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                        ; To                                                                                                                                   ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 7.826 ns                         ; load                                                                                                        ; piso:s2|po[14]                                                                                                                       ;                              ; sck                          ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 9.052 ns                         ; sin_rom:s3|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[0] ; fout[0]                                                                                                                              ; clk                          ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                    ; altera_reserved_tdo                                                                                                                  ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 3.372 ns                         ; altera_internal_jtag~TMSUTAP                                                                                ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1]                                                              ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case Minimum tco                      ; N/A   ; None          ; 7.546 ns                         ; sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|q_a[3] ; pout[3]                                                                                                                              ; clk                          ;                              ; 0            ;
; Worst-case Minimum tpd                      ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                    ; altera_reserved_tdo                                                                                                                  ;                              ;                              ; 0            ;
; Clock Setup: 'clk'                          ; N/A   ; None          ; 79.88 MHz ( period = 12.518 ns ) ; add:s4|stand[3]                                                                                             ; sin_rom:s5|altsyncram:altsyncram_component|altsyncram_qjs:auto_generated|altsyncram_gaa2:altsyncram1|ram_block3a7~porta_address_reg3 ; clk                          ; clk                          ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 107.25 MHz ( period = 9.324 ns ) ; sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]                                                     ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                                                                                    ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'sck'                          ; N/A   ; None          ; 195.43 MHz ( period = 5.117 ns ) ; piso:s2|lpm_counter:i_rtl_0|cntr_fa7:auto_generated|safe_q[1]                                               ; piso:s2|po[1]                                                                                                                        ; sck                          ; sck                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                             ;                                                                                                                                      ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                            ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk                          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; load                         ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; sck                          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+