xc2v_distri_ram_64s.v

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//
// Module: 	XC2V_DISTRI_RAM_64S
//
// Description: Distributed SelectRAM example
//		Single Port 64 x 1
//		Use template "SelectRAM_64S.v"
//
// Device: 	VIRTEX-II Family
//-----------------------------------------------------------------------------------------------------

module XC2V_DISTRI_RAM_64S (DATA_IN, ADDRESS, WRITE_EN, CLK, O_DATA_OUT_64);

input DATA_IN;
input [5:0] ADDRESS;
input WRITE_EN;
input CLK;

output O_DATA_OUT_64;
reg O_DATA_OUT_64;

wire CLK_BUFG;
wire DATA_OUT_64;


// synopsys translate_off
defparam 
	//RAM initialization ("0" by default) for functional simulation:
	U_RAM64X1S.INIT = 64'h0000000000000000;
// synopsys translate_on


//Instantiate the clock Buffer
BUFG U_BUFG (  .I(CLK), .O(CLK_BUFG));


//Distributed SelectRAM Instantiation
RAM64X1S U_RAM64X1S  (  .D(DATA_IN),       //insert input signal
			.WE(WRITE_EN),     //insert Write Enable signal
			.WCLK(CLK_BUFG),   //insert Write Clock signal
			.A0(ADDRESS[0]),   //insert Address 0 signal
			.A1(ADDRESS[1]),   //insert Address 1 signal
			.A2(ADDRESS[2]),   //insert Address 2 signal
			.A3(ADDRESS[3]),   //insert Address 3 signal
			.A4(ADDRESS[4]),   //insert Address 4 signal
			.A5(ADDRESS[5]),   //insert Address 5 signal
			.O(DATA_OUT_64)    //insert output signal
		      );
 

//Registered outputs / Synchronous read
always @(posedge CLK_BUFG)

  O_DATA_OUT_64 <= DATA_OUT_64;



// synthesis attribute declarations
  /* synopsys attribute 

	INIT "0000000000000000"
  */	

endmodule