selectram_16s.v

来自「本人正在学习vhdl语言」· Verilog 代码 · 共 38 行

//
// Module: 	SelectRAM_16S 
//
// Description: Verilog instantiation template
//		Distributed SelectRAM
//		Single Port 16 x 1
//		can be used also for RAM16X1S_1
//
// Device: 	VIRTEX-II Family 
//-------------------------------------------------------------------------------------------
//
//
// Syntax for Synopsys FPGA Express
// synopsys translate_off

  defparam  

  //RAM initialization ("0" by default) for functional simulation:
  U_RAM16X1S.INIT = 16'h0000; 
// synopsys translate_on	


//Distributed SelectRAM Instantiation
RAM16X1S U_RAM16X1S (  .D(),      // insert input signal 
	               .WE(),     // insert Write Enable signal
	               .WCLK(),   // insert Write Clock signal
	               .A0(),     // insert Address 0 signal
	               .A1(),     // insert Address 1 signal
	               .A2(),     // insert Address 2 signal
	               .A3(),     // insert Address 3 signal
	               .O()       // insert output signal
	                );

// synthesis attribute declarations
  /* synopsys attribute 

	INIT "0000"
  */