selectram_32d.v

来自「本人正在学习vhdl语言」· Verilog 代码 · 共 45 行

//
// Module: 	SelectRAM_32D  
//
// Description: Verilog instantiation template
//		Distributed SelectRAM
//		Dual Port 32 x 1
//		can be used also for RAM32X1D_1
//
// Device: 	VIRTEX-II Family 
//-------------------------------------------------------------------------------------------
//
//
// Syntax for Synopsys FPGA Express
// synopsys translate_off

  defparam  

  //RAM initialization ("0" by default) for functional simulation:
  U_RAM32X1D.INIT = 32'h00000000; 
// synopsys translate_on	


//Distributed SelectRAM Instantiation
RAM32X1D U_RAM32X1D (  .D(),      // insert input signal 
	               .WE(),     // insert Write Enable signal
	               .WCLK(),   // insert Write Clock signal
	               .A0(),     // insert Address 0 signal port SPO
	               .A1(),     // insert Address 1 signal port SPO
	               .A2(),     // insert Address 2 signal port SPO
	               .A3(),     // insert Address 3 signal port SPO
		       .A4(),     // insert Address 4 signal port SPO
	               .DPRA0(),  // insert Address 0 signal port DPO
		       .DPRA1(),  // insert Address 1 signal port DPO
 	               .DPRA2(),  // insert Address 2 signal port DPO
	               .DPRA3(),  // insert Address 3 signal port DPO
		       .DPRA4(),  // insert Address 4 signal port DPO
	               .SPO(),    // insert output signal
	               .DPO()     // insert output signal 
	                );

// synthesis attribute declarations
  /* synopsys attribute 

	INIT "00000000"
  */