selectram_32s.v

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//
// Module: 	SelectRAM_32S
//
// Description: Verilog instantiation template
//		Distributed SelectRAM
//		Single Port 32 x 1
//		can be used also for RAM32X1S_1
//
// Device: 	VIRTEX-II Family 
//-------------------------------------------------------------------------------------------
//
//
// Syntax for Synopsys FPGA Express
// synopsys translate_off

  defparam  

  //RAM initialization ("0" by default) for functional simulation:
  U_RAM32X1S.INIT = 32'h00000000;
// synopsys translate_on	


//Distributed SelectRAM Instantiation
RAM32X1S U_RAM32X1S  (  .D(),    //insert input signal
			.WE(),   //insert Write Enable signal
			.WCLK(), //insert Write Clock signal
			.A0(),   //insert Address 0 signal
			.A1(),   //insert Address 1 signal
			.A2(),   //insert Address 2 signal
			.A3(),   //insert Address 3 signal
			.A4(),   //insert Address 4 signal
			.O()     //insert output signal
		      );

// synthesis attribute declarations
  /* synopsys attribute 

	INIT "00000000"
  */