xc2v_ram64xn_d.v

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//
// Module: 	XC2V_RAM64XN_D
//
// Description: Distributed SelectRAM example
//		Dual Port 64 x N-bit
//		Use template "SelectRAM_64D.v"
//		and registered outputs (optional)
//
// Device: 	VIRTEX-II Family
//---------------------------------------------------------------------------------------

module XC2V_RAM364XN_D (DATA_IN, ADDRESS, ADDRESS_DP, WRITE_EN, CLK, O_DATA_OUT, O_DATA_OUT_DP);

parameter data_width = 8;//Replace with desired data-bus width 
                         
input [data_width-1:0]DATA_IN;
input [5:0] ADDRESS;
input [5:0] ADDRESS_DP;
input WRITE_EN;
input CLK;

output [data_width-1:0]O_DATA_OUT_DP;
reg    [data_width-1:0]O_DATA_OUT_DP;
output [data_width-1:0]O_DATA_OUT;
reg    [data_width-1:0]O_DATA_OUT;

wire [data_width-1:0]DATA_OUT;
wire [data_width-1:0]DATA_OUT_DP;


/*Remember to Instantiate a Distributed SelectRAM block for each Data port
  and to give each instance a unique name...The following is an example of instantiation 
  for a 64 X 8-bit RAM. */

//Distributed SelectRAM Instantiation - Data-Port 0	
 
   RAM64X1D U_RAM64X1D_0(  .D(DATA_IN[0]),        //insert input signal
       			   .WE(WRITE_EN),         //insert Write Enable signal
			   .WCLK(CLK),            //insert Write Clock signal
			   .A0(ADDRESS[0]),       //insert Address 0 signal port SPO
			   .A1(ADDRESS[1]),       //insert Address 1 signal port SPO
			   .A2(ADDRESS[2]),       //insert Address 2 signal port SPO
			   .A3(ADDRESS[3]),       //insert Address 3 signal port SPO
			   .A4(ADDRESS[4]),       //insert Address 4 signal port SPO
			   .A5(ADDRESS[5]),       //insert Address 5 signal port SPO
			   .DPRA0(ADDRESS_DP[0]), //insert Address 0 signal dual port DPO
			   .DPRA1(ADDRESS_DP[1]), //insert Address 1 signal dual port DPO
			   .DPRA2(ADDRESS_DP[2]), //insert Address 2 signal dual port DPO
			   .DPRA3(ADDRESS_DP[3]), //insert Address 3 signal dual port DPO
			   .DPRA4(ADDRESS_DP[4]), //insert Address 4 signal dual port DPO
			   .DPRA5(ADDRESS_DP[5]), //insert Address 5 signal dual port DPO
			   .SPO(DATA_OUT[0]),     //insert output signal SPO
			   .DPO(DATA_OUT_DP[0])   //insert output signal DPO
		         );

//Distributed SelectRAM Instantiation - Data-Port 1		
 
  RAM64X1D U_RAM64X1D_1(   .D(DATA_IN[1]),        //insert input signal
       			   .WE(WRITE_EN),         //insert Write Enable signal
			   .WCLK(CLK),            //insert Write Clock signal
			   .A0(ADDRESS[0]),       //insert Address 0 signal port SPO
			   .A1(ADDRESS[1]),       //insert Address 1 signal port SPO
			   .A2(ADDRESS[2]),       //insert Address 2 signal port SPO
			   .A3(ADDRESS[3]),       //insert Address 3 signal port SPO
			   .A4(ADDRESS[4]),       //insert Address 4 signal port SPO
			   .A5(ADDRESS[5]),       //insert Address 5 signal port SPO
			   .DPRA0(ADDRESS_DP[0]), //insert Address 0 signal dual port DPO
			   .DPRA1(ADDRESS_DP[1]), //insert Address 1 signal dual port DPO
			   .DPRA2(ADDRESS_DP[2]), //insert Address 2 signal dual port DPO
			   .DPRA3(ADDRESS_DP[3]), //insert Address 3 signal dual port DPO
			   .DPRA4(ADDRESS_DP[4]), //insert Address 4 signal dual port DPO
			   .DPRA5(ADDRESS_DP[5]), //insert Address 5 signal dual port DPO
			   .SPO(DATA_OUT[1]),     //insert output signal SPO
			   .DPO(DATA_OUT_DP[1])   //insert output signal DPO
		         );

//Distributed SelectRAM Instantiation - Data-Port 2		
 RAM64X1D U_RAM64X1D_2(    .D(DATA_IN[2]),        //insert input signal
       			   .WE(WRITE_EN),         //insert Write Enable signal
			   .WCLK(CLK),            //insert Write Clock signal
			   .A0(ADDRESS[0]),       //insert Address 0 signal port SPO
			   .A1(ADDRESS[1]),       //insert Address 1 signal port SPO
			   .A2(ADDRESS[2]),       //insert Address 2 signal port SPO
			   .A3(ADDRESS[3]),       //insert Address 3 signal port SPO
			   .A4(ADDRESS[4]),       //insert Address 4 signal port SPO
			   .A5(ADDRESS[5]),       //insert Address 5 signal port SPO
			   .DPRA0(ADDRESS_DP[0]), //insert Address 0 signal dual port DPO
			   .DPRA1(ADDRESS_DP[1]), //insert Address 1 signal dual port DPO
			   .DPRA2(ADDRESS_DP[2]), //insert Address 2 signal dual port DPO
			   .DPRA3(ADDRESS_DP[3]), //insert Address 3 signal dual port DPO
			   .DPRA4(ADDRESS_DP[4]), //insert Address 4 signal dual port DPO
			   .DPRA5(ADDRESS_DP[5]), //insert Address 5 signal dual port DPO
			   .SPO(DATA_OUT[2]),     //insert output signal SPO
			   .DPO(DATA_OUT_DP[2])   //insert output signal DPO
		         );


//Distributed SelectRAM Instantiation - Data-Port 3		
 
  RAM64X1D U_RAM64X1D_3(   .D(DATA_IN[3]),        //insert input signal
       			   .WE(WRITE_EN),         //insert Write Enable signal
			   .WCLK(CLK),            //insert Write Clock signal
			   .A0(ADDRESS[0]),       //insert Address 0 signal port SPO
			   .A1(ADDRESS[1]),       //insert Address 1 signal port SPO
			   .A2(ADDRESS[2]),       //insert Address 2 signal port SPO
			   .A3(ADDRESS[3]),       //insert Address 3 signal port SPO
			   .A4(ADDRESS[4]),       //insert Address 4 signal port SPO
			   .A5(ADDRESS[5]),       //insert Address 5 signal port SPO
			   .DPRA0(ADDRESS_DP[0]), //insert Address 0 signal dual port DPO
			   .DPRA1(ADDRESS_DP[1]), //insert Address 1 signal dual port DPO
			   .DPRA2(ADDRESS_DP[2]), //insert Address 2 signal dual port DPO
			   .DPRA3(ADDRESS_DP[3]), //insert Address 3 signal dual port DPO
			   .DPRA4(ADDRESS_DP[4]), //insert Address 4 signal dual port DPO
			   .DPRA5(ADDRESS_DP[5]), //insert Address 5 signal dual port DPO
			   .SPO(DATA_OUT[3]),     //insert output signal SPO
			   .DPO(DATA_OUT_DP[3])   //insert output signal DPO
		         );
 	

//Distributed SelectRAM Instantiation - Data-Port 4		
 
  RAM64X1D U_RAM64X1D_4(   .D(DATA_IN[4]),        //insert input signal
       			   .WE(WRITE_EN),         //insert Write Enable signal
			   .WCLK(CLK),            //insert Write Clock signal
			   .A0(ADDRESS[0]),       //insert Address 0 signal port SPO
			   .A1(ADDRESS[1]),       //insert Address 1 signal port SPO
			   .A2(ADDRESS[2]),       //insert Address 2 signal port SPO
			   .A3(ADDRESS[3]),       //insert Address 3 signal port SPO
			   .A4(ADDRESS[4]),       //insert Address 4 signal port SPO
			   .A5(ADDRESS[5]),       //insert Address 5 signal port SPO
			   .DPRA0(ADDRESS_DP[0]), //insert Address 0 signal dual port DPO
			   .DPRA1(ADDRESS_DP[1]), //insert Address 1 signal dual port DPO
			   .DPRA2(ADDRESS_DP[2]), //insert Address 2 signal dual port DPO
			   .DPRA3(ADDRESS_DP[3]), //insert Address 3 signal dual port DPO
			   .DPRA4(ADDRESS_DP[4]), //insert Address 4 signal dual port DPO
			   .DPRA5(ADDRESS_DP[5]), //insert Address 5 signal dual port DPO
			   .SPO(DATA_OUT[4]),     //insert output signal SPO
			   .DPO(DATA_OUT_DP[4])   //insert output signal DPO
		         );

//Distributed SelectRAM Instantiation - Data-Port 5		
 
  RAM64X1D U_RAM64X1D_5(   .D(DATA_IN[5]),        //insert input signal
       			   .WE(WRITE_EN),         //insert Write Enable signal
			   .WCLK(CLK),            //insert Write Clock signal
			   .A0(ADDRESS[0]),       //insert Address 0 signal port SPO
			   .A1(ADDRESS[1]),       //insert Address 1 signal port SPO
			   .A2(ADDRESS[2]),       //insert Address 2 signal port SPO
			   .A3(ADDRESS[3]),       //insert Address 3 signal port SPO
			   .A4(ADDRESS[4]),       //insert Address 4 signal port SPO
			   .A5(ADDRESS[5]),       //insert Address 5 signal port SPO
			   .DPRA0(ADDRESS_DP[0]), //insert Address 0 signal dual port DPO
			   .DPRA1(ADDRESS_DP[1]), //insert Address 1 signal dual port DPO
			   .DPRA2(ADDRESS_DP[2]), //insert Address 2 signal dual port DPO
			   .DPRA3(ADDRESS_DP[3]), //insert Address 3 signal dual port DPO
			   .DPRA4(ADDRESS_DP[4]), //insert Address 4 signal dual port DPO
			   .DPRA5(ADDRESS_DP[5]), //insert Address 5 signal dual port DPO
			   .SPO(DATA_OUT[5]),     //insert output signal SPO
			   .DPO(DATA_OUT_DP[5])   //insert output signal DPO
		         );

//Distributed SelectRAM Instantiation - Data-Port 6		
 
  RAM64X1D U_RAM64X1D_6(   .D(DATA_IN[6]),        //insert input signal
       			   .WE(WRITE_EN),         //insert Write Enable signal
			   .WCLK(CLK),            //insert Write Clock signal
			   .A0(ADDRESS[0]),       //insert Address 0 signal port SPO
			   .A1(ADDRESS[1]),       //insert Address 1 signal port SPO
			   .A2(ADDRESS[2]),       //insert Address 2 signal port SPO
			   .A3(ADDRESS[3]),       //insert Address 3 signal port SPO
			   .A4(ADDRESS[4]),       //insert Address 4 signal port SPO
			   .A5(ADDRESS[5]),       //insert Address 5 signal port SPO
			   .DPRA0(ADDRESS_DP[0]), //insert Address 0 signal dual port DPO
			   .DPRA1(ADDRESS_DP[1]), //insert Address 1 signal dual port DPO
			   .DPRA2(ADDRESS_DP[2]), //insert Address 2 signal dual port DPO
			   .DPRA3(ADDRESS_DP[3]), //insert Address 3 signal dual port DPO
			   .DPRA4(ADDRESS_DP[4]), //insert Address 4 signal dual port DPO
			   .DPRA5(ADDRESS_DP[5]), //insert Address 5 signal dual port DPO
			   .SPO(DATA_OUT[6]),     //insert output signal SPO
			   .DPO(DATA_OUT_DP[6])   //insert output signal DPO
		         );


//Distributed SelectRAM Instantiation - Data-Port 7	
 
  RAM64X1D U_RAM64X1D_7(   .D(DATA_IN[7]),        //insert input signal
       			   .WE(WRITE_EN),         //insert Write Enable signal
			   .WCLK(CLK),            //insert Write Clock signal
			   .A0(ADDRESS[0]),       //insert Address 0 signal port SPO
			   .A1(ADDRESS[1]),       //insert Address 1 signal port SPO
			   .A2(ADDRESS[2]),       //insert Address 2 signal port SPO
			   .A3(ADDRESS[3]),       //insert Address 3 signal port SPO
			   .A4(ADDRESS[4]),       //insert Address 4 signal port SPO
			   .A5(ADDRESS[5]),       //insert Address 5 signal port SPO
			   .DPRA0(ADDRESS_DP[0]), //insert Address 0 signal dual port DPO
			   .DPRA1(ADDRESS_DP[1]), //insert Address 1 signal dual port DPO
			   .DPRA2(ADDRESS_DP[2]), //insert Address 2 signal dual port DPO
			   .DPRA3(ADDRESS_DP[3]), //insert Address 3 signal dual port DPO
			   .DPRA4(ADDRESS_DP[4]), //insert Address 4 signal dual port DPO
			   .DPRA5(ADDRESS_DP[5]), //insert Address 5 signal dual port DPO
			   .SPO(DATA_OUT[7]),     //insert output signal SPO
			   .DPO(DATA_OUT_DP[7])   //insert output signal DPO
		         );



//Registered outputs / Synchronous read
always @(posedge CLK)

begin
  O_DATA_OUT <= DATA_OUT;
  O_DATA_OUT_DP <= DATA_OUT_DP;
end

endmodule