coregen.log

来自「用Verilog HDL 语言编写的播放梁祝的程序」· LOG 代码 · 共 22 行

# Xilinx CORE Generator 6.3.03i
# User = Inshine Lau
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in F:\EDA试验\music\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=F:\EDA试验\music
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=F:\EDA试验\music
SETPROJECT .
Set current Project to F:\EDA试验\music
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 3009
XIPCPJSENDCORES spartan2