play.syr

用Verilog HDL 语言编写的播放梁祝的程序

RTL Top Level Output File Name     : play.ngr
Top Level Output File Name         : play
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 2

Macro Statistics :
# Registers                        : 9
#      1-bit register              : 3
#      14-bit register             : 1
#      21-bit register             : 2
#      24-bit register             : 2
#      8-bit register              : 1
# Counters                         : 1
#      14-bit up counter           : 1
# Adders/Subtractors               : 3
#      24-bit adder                : 2
#      8-bit adder                 : 1

Cell Usage :
# BELS                             : 317
#      GND                         : 1
#      LUT1                        : 52
#      LUT1_L                      : 7
#      LUT2                        : 13
#      LUT2_D                      : 1
#      LUT2_L                      : 2
#      LUT3                        : 32
#      LUT4                        : 48
#      LUT4_D                      : 4
#      LUT4_L                      : 21
#      MUXCY                       : 67
#      MUXF5                       : 1
#      VCC                         : 1
#      XORCY                       : 67
# FlipFlops/Latches                : 105
#      FD                          : 17
#      FDE                         : 17
#      FDR                         : 49
#      FDS                         : 22
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 1
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100tq144-5 

 Number of Slices:                     109  out of   1200     9%  
 Number of Slice Flip Flops:           105  out of   2400     4%  
 Number of 4 input LUTs:               180  out of   2400     7%  
 Number of bonded IOBs:                  1  out of     96     1%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_4Hz:Q                          | NONE                   | 40    |
clk_6MHz:Q                         | NONE                   | 15    |
sys_CLK                            | BUFGP                  | 50    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 14.341ns (Maximum Frequency: 69.730MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 8.189ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk_4Hz:Q'
Delay:               14.341ns (Levels of Logic = 6)
  Source:            len_0 (FF)
  Destination:       j_5 (FF)
  Source Clock:      clk_4Hz:Q rising
  Destination Clock: clk_4Hz:Q rising

  Data Path: len_0 to j_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             19   1.292   3.100  len_0 (len_0)
     LUT1_L:I0->LO         1   0.653   0.000  play__n0011<0>lut (N1960)
     MUXCY:S->O            1   0.784   0.000  play__n0011<0>cy (play__n0011<0>_cyo)
     XORCY:CI->O          18   0.500   3.000  play__n0011<1>_xor (_n0011<1>)
     LUT4:I0->O            1   0.653   1.150  _n0005<5>1371_SW1_SW0 (N6434)
     LUT4:I3->O            1   0.653   1.150  _n0005<5>1371_SW1 (N6422)
     LUT4_L:I2->LO         1   0.653   0.000  _n0005<5>1371 (N6153)
     FDS:D                     0.753          j_5
    ----------------------------------------
    Total                     14.341ns (5.941ns logic, 8.400ns route)
                                       (41.4% logic, 58.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk_6MHz:Q'
Delay:               11.178ns (Levels of Logic = 17)
  Source:            count_10 (FF)
  Destination:       count_13 (FF)
  Source Clock:      clk_6MHz:Q rising
  Destination Clock: clk_6MHz:Q rising

  Data Path: count_10 to count_13
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   1.292   1.340  count_10 (count_10)
     LUT2:I0->O            1   0.653   1.150  _n00070 (CHOICE117)
     LUT4:I0->O           16   0.653   2.800  _n000729 (_n0007)
     LUT3:I0->O            1   0.653   0.000  count_inst_lut3_01 (count_inst_lut3_0)
     MUXCY:S->O            1   0.784   0.000  count_inst_cy_1 (count_inst_cy_1)
     MUXCY:CI->O           1   0.050   0.000  count_inst_cy_2 (count_inst_cy_2)
     MUXCY:CI->O           1   0.050   0.000  count_inst_cy_3 (count_inst_cy_3)
     MUXCY:CI->O           1   0.050   0.000  count_inst_cy_4 (count_inst_cy_4)
     MUXCY:CI->O           1   0.050   0.000  count_inst_cy_5 (count_inst_cy_5)
     MUXCY:CI->O           1   0.050   0.000  count_inst_cy_6 (count_inst_cy_6)
     MUXCY:CI->O           1   0.050   0.000  count_inst_cy_7 (count_inst_cy_7)
     MUXCY:CI->O           1   0.050   0.000  count_inst_cy_8 (count_inst_cy_8)
     MUXCY:CI->O           1   0.050   0.000  count_inst_cy_9 (count_inst_cy_9)
     MUXCY:CI->O           1   0.050   0.000  count_inst_cy_10 (count_inst_cy_10)
     MUXCY:CI->O           1   0.050   0.000  count_inst_cy_11 (count_inst_cy_11)
     MUXCY:CI->O           1   0.050   0.000  count_inst_cy_12 (count_inst_cy_12)
     MUXCY:CI->O           0   0.050   0.000  count_inst_cy_13 (count_inst_cy_13)
     XORCY:CI->O           1   0.500   0.000  count_inst_sum_13 (count_inst_sum_13)
     FDE:D                     0.753          count_13
    ----------------------------------------
    Total                     11.178ns (5.888ns logic, 5.290ns route)
                                       (52.7% logic, 47.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'sys_CLK'
Delay:               11.227ns (Levels of Logic = 3)
  Source:            counter4Hz_14 (FF)
  Destination:       clk_4Hz (FF)
  Source Clock:      sys_CLK rising
  Destination Clock: sys_CLK rising

  Data Path: counter4Hz_14 to clk_4Hz
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   1.292   1.340  counter4Hz_14 (counter4Hz_14)
     LUT4:I0->O            1   0.653   1.150  _n000179 (CHOICE113)
     LUT3:I0->O            1   0.653   1.150  _n0001105_SW0 (N6452)
     LUT4:I3->O           25   0.653   3.450  _n0001105 (_n0001)
     FDE:CE                    0.886          clk_4Hz
    ----------------------------------------
    Total                     11.227ns (4.137ns logic, 7.090ns route)
                                       (36.8% logic, 63.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_6MHz:Q'
Offset:              8.189ns (Levels of Logic = 1)
  Source:            audiof (FF)
  Destination:       audiof (PAD)
  Source Clock:      clk_6MHz:Q rising

  Data Path: audiof to audiof
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   1.292   1.340  audiof (audiof_OBUF)
     OBUF:I->O                 5.557          audiof_OBUF (audiof)
    ----------------------------------------
    Total                      8.189ns (6.849ns logic, 1.340ns route)
                                       (83.6% logic, 16.4% route)

=========================================================================
CPU : 6.72 / 8.17 s | Elapsed : 7.00 / 8.00 s
 
--> 

Total memory usage is 59144 kilobytes