divf_test.v.bak

用Verilog HDL 语言编写的播放梁祝的程序

`define auto_init
`timescale 1ns/1ns

module divf_divf_test_v_tf();
    reg CLK;
    reg CLR;
    reg [31:0] sysf;
    reg [31:0] divf;
    wire divf_CLK;
    integer i;
    integer max;

divf divf_test(divf_CLK,CLK,CLR,sysf,divf);

    `ifdef auto_init

        initial begin
            CLK = 0;
            CLR=1;
            sysf = 20;
            divf = 5;
		      max=1000;  
        end

    `endif

	initial
	begin
     	for(i=1;i<max;i=i+1)
			#1 CLK=~CLK;
	end




endmodule