lfsr_sim.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		LFSR simulation
//
// FILE NAME:	lfsr_sim.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Simulation
//
// DESCRIPTION:	This module provides stimuli for simulating
// a Linear Feedback Shift Register. This simulation cycles
// for the full number of cycles and checks that we get the
// initial value again exactly at the end of the sequence,
// not sooner or later.
//
/*********************************************************/

// DEFINES
`define DEL	1		// Clock-to-output delay. Zero
					// time delays can be confusing
					// and sometimes cause problems.

`define BITS 8		// Number of bits in the LFSR

// TOP MODULE
module lfsr_sim();

// INPUTS

// OUTPUTS

// INOUTS

// SIGNAL DECLARATIONS
reg					clock;
reg					reset;
wire [`BITS-1:0]	data;

integer		cycle_count;	// Cycle count variable
integer		cycle_limit;	// The number of cycles to
							// simulate
integer		init_value;		// Used to store the
							// initial value of LFSR

// PARAMETERS

// ASSIGN STATEMENTS

// MAIN CODE

// Instantiate the counter
LFSR lfsr(
	   	.clk(clock),
	   	.reset(reset),
		.data(data));

// Initialize inputs
initial begin
	clock = 1;
	reset = 0;
	cycle_count = 0;

`ifdef ADD_ZERO			// Use this code if a data == 0 is required
	$display ("Simulation with zero value added to sequence\n");
	cycle_limit = (32'h00000001 << `BITS);
`else					// Use this code for a standard LFSR
	cycle_limit = (32'h00000001 << `BITS)-1;
`endif

	// Reset the LFSR and record the initial value
	#10 reset = 1;
	#10 reset = 0;
	init_value <= data;
end

// Generate the clock
always #100 clock = ~clock;

// Simulate
always @(posedge clock) begin
	// Wait for outputs to settle
	#`DEL;
	#`DEL;

	// Increment the cycle count
	cycle_count = cycle_count + 1;

	// Check whether we have cycled back to the
	// original value
	if (data === init_value) begin
		if (cycle_count === cycle_limit) begin
			$display("\nSimulation complete - no errors\n");
			$finish;
		end
		else begin
			$display("\nERROR at time %0t:", $time);
			$display("LFSR cycled too quickly");
			$display("    initial value = %h", init_value);
			$display("    current value = %h", data);
			$display("    cycle count   = %d\n", cycle_count);

			// Use $stop for debugging
			$stop;
		end
	end
	else if (cycle_count === cycle_limit) begin
		$display("\nERROR at time %0t:", $time);
		$display("LFSR should have cycled by now");
		$display("    initial value = %h", init_value);
		$display("    current value = %h", data);
		$display("    cycle count   = %d\n", cycle_count);

		// Use $stop for debugging
		$stop;
	end
end
endmodule		// lfsr_sim