ram.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		RAM
//
// FILE NAME:	ram.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Behavioral and RTL
//
// DESCRIPTION:	This module defines a Random Access Memory.
//
/*********************************************************/

// DEFINES
`define DEL	1			// Clock-to-output delay. Zero
						// time delays can be confusing
						// and sometimes cause problems.

`define RAM_WIDTH 8		// Width of RAM (number of bits)
`define RAM_DEPTH 16	// Depth of RAM (number of bytes)
`define ADDR_SZ 4		// Number of bits required to
						// represent the RAM address

// TOP MODULE
module Ram(
		data,
		address,
		write_n,
		oe_n);

// INPUTS
input [`ADDR_SZ-1:0] address; 	// RAM address
input				 write_n;  	// Write strobe (active low)
input				 oe_n; 		// Output enable (active low)

// OUTPUTS

// INOUTS
inout [`RAM_WIDTH-1:0]	data;	// RAM data

// SIGNAL DECLARATIONS
wire [`ADDR_SZ-1:0] 	address;
wire					write_n;
wire					oe_n;
wire [`RAM_WIDTH-1:0]	data;

								// The RAM
reg  [`RAM_WIDTH-1:0]	mem [`RAM_DEPTH-1:0];
// PARAMETERS

// ASSIGN STATEMENTS
assign #`DEL data = oe_n ? `RAM_WIDTH'bz : mem[address];

// MAIN CODE

// Look at the rising edge of the write signal
always @(posedge write_n) begin
	mem[address] = data;
end
endmodule		// Ram