par_sim.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		parity generator/checker simulation
//
// FILE NAME:	par_sim.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Simulation
//
// DESCRIPTION:	This module provides stimuli for simulating
// a parity generator and checker. It tests a large number of
// random data words using odd parity, then a random number
// of data words using even parity. It then forces errors and
// checks that the bad data words are correctly signaled by
// error output.
//
/*********************************************************/

// DEFINES
`define CYCLE_NUM 100	// Number of cycles per test to
						// perform

// TOP MODULE
module par_sim();

// INPUTS

// OUTPUTS

// INOUTS

// SIGNAL DECLARATIONS
reg  [31:0]	data;
reg  [3:0]	parity_in;
reg			even_odd;
wire [3:0]	parity_out;
wire [3:0]	error;

reg			clock;
integer		cycle_count;	// Counter for simulation events
reg			force_error;	// Force an error on the input parity

// PARAMETERS

// ASSIGN STATEMENTS

// MAIN CODE

// Instantiate the parity generator/checker
Parity parity(
		.data(data),
		.par_in(parity_in),
		.even_odd(even_odd),
		.par_out(parity_out),
		.error(error));

// Initialize inputs
initial begin
	cycle_count = 0;
	clock = 1;
	even_odd = 0;		// Look at odd parity first
	force_error = 0;	// Do not force a parity error on inputs
	$random(0);	   		// Initialize random number generator
end

// Generate the clock
always #100 clock = ~clock;

// Simulate
// Set up the inputs on the falling edge of the clock
always @(negedge clock) begin
	case (cycle_count)
		`CYCLE_NUM:	begin
			// Switch the even/odd input
			even_odd = ~even_odd;
		end
		2*`CYCLE_NUM: begin
			// Force an error to check that the error
			// output is asserted
			force_error = 1;
		end
		3*`CYCLE_NUM: begin
			$display("\nSimulation complete - no errors\n");
			$finish;
		end
	endcase

	data = {$random} % 32'hFFFFFFFF;
	if (even_odd ^ force_error) begin
		parity_in[3] = ^data[31:24];
		parity_in[2] = ^data[23:16];
		parity_in[1] = ^data[15:8];
		parity_in[0] = ^data[7:0];
	end
	else begin
		parity_in[3] = ~^data[31:24];
		parity_in[2] = ~^data[23:16];
		parity_in[1] = ~^data[15:8];
		parity_in[0] = ~^data[7:0];
	end
end

// Check the outputs on the rising edge of the clock
always @(posedge clock) begin
	if (~force_error) begin
		if (parity_in !== parity_out) begin
			$display("\nERROR at time %0t:", $time);
			$display("Output parity is incorrect");
			$display("    expected = %h", parity_in);
			$display("    actual   = %h\n", parity_out);
		
			// Use $stop for debugging
			$stop;
		end
		if (error !== 0) begin
			$display("\nERROR at time %0t:", $time);
			$display("Error signal is asserted");
			$display("    error = %b\n", error);
		
			// Use $stop for debugging
			$stop;
		end
	end
	else begin
		if (parity_in !== ~parity_out) begin
			$display("\nERROR at time %0t:", $time);
			$display("Output parity is incorrect");
			$display("    expected = %h", ~parity_in);
			$display("    actual   = %h\n", parity_out);
		
			// Use $stop for debugging
			$stop;
		end
		if (error === 0) begin
			$display("\nERROR at time %0t:", $time);
			$display("Error signal is not asserted\n");
		
			// Use $stop for debugging
			$stop;
		end
	end

	// Increment the cycle count
	cycle_count = cycle_count + 1;
end
endmodule		// par_sim