shift_sim.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		barrel shifter simulation
//
// FILE NAME:	shift_sim.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Simulation
//
// DESCRIPTION:	This module provides stimuli for simulating
// a barrel shifter. It performs a number of right shifts and
// left shifts and compares the actual output to the expected
// output. It also tests that data can be loaded into the
// shifter, and that a shift of zero places correctly results
// in no shift at all.
//
/*********************************************************/

// DEFINES

// TOP MODULE
module shift_sim();

// INPUTS

// OUTPUTS

// INOUTS

// SIGNAL DECLARATIONS
reg			clock;
reg		   	load;
reg		   	rshift;
reg		   	lshift;
reg  [2:0] 	numbits;
reg		   	shift_in;
reg  [7:0] 	in_data;
wire [7:0] 	out_data;

reg  [7:0]	expected_data;	// Expected data output
reg  [7:0]	previous_data;	// Previous data output
integer		cycle_count;	// Counter for simulation events

// PARAMETERS

// ASSIGN STATEMENTS

// MAIN CODE

// Instantiate the parity generator/checker
Shifter shifter(
		.clk(clock),
		.load(load),
		.rshift(rshift),
		.lshift(lshift),
		.shiftnum(numbits),
		.inbit(shift_in),
		.in(in_data),
		.out(out_data));

// Initialize inputs
initial begin
	cycle_count = 0;
	clock = 0;
	load = 0;
	rshift = 0;
	lshift = 0;
end

// Generate the clock
always #100 clock = ~clock;

// Simulate
// Set up the inputs on the falling edge of the clock
always @(negedge clock) begin
	// Check the data output against the expected output
	if (out_data !== expected_data) begin
		$display("\nERROR at time %0t:", $time);
		$display("Output data is incorrect");
		$display("    load input      = %b", load);
		$display("    rshift input    = %b", rshift);
		$display("    lshift input    = %b", lshift);
		$display("    numbits input   = %h", numbits);
		$display("    input bit       = %b", shift_in);
		$display("    input data      = %h", in_data);
		$display("    previous output = %h", previous_data);
		$display("    expected output = %h", expected_data);
		$display("    actual output   = %h\n", out_data);
	
		// Use $stop for debugging
		$stop;
	end

	case (cycle_count)
		1:	begin				// Load data
			in_data = 8'b10101010;
			expected_data = 8'b10101010;
			load = 1'b1;
		end
		2: begin				// Shift right
			in_data = 8'bx;
			shift_in = 1'b1;
			numbits = 3'h3;
			expected_data = 8'b11110101;
			load = 1'b0;
			rshift = 1'b1;
		end
		3: begin				// Shift right
			shift_in = 1'b0;
			numbits = 3'h1;
			expected_data = 8'b01111010;
		end
		4: begin				// Shift right
			numbits = 3'h0;
			expected_data = 8'b01111010;
		end
		5: begin				// Shift right
			shift_in = 1'b1;
			numbits = 3'h7;
			expected_data = 8'b11111110;
		end
		6: begin				// Shift left
			shift_in = 1'b0;
			rshift = 1'b0;
			lshift = 1'b1;
			numbits = 3'h2;
			expected_data = 8'b11111000;
		end
		7: begin				// Shift left
			shift_in = 1'b1;
			numbits = 3'h5;
			expected_data = 8'b00011111;
		end
		8:	begin				// Load data
			in_data = 8'b11000011;
			expected_data = 8'b11000011;
			load = 1'b1;
		end
		9: begin
			$display("\nSimulation complete - no errors\n");
			$finish;
		end
	endcase

	// Record the previous data output
	previous_data = out_data;

	// Increment the cycle count
	cycle_count = cycle_count + 1;
end
endmodule		// shift_sim