checksum.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		Checksum generator and verifier
//
// FILE NAME:	checksum.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Behavioral and RTL
//
// DESCRIPTION:	This module defines a checksum generator
// and verifier. To generate the checksum the internal
// accumulator must first be cleared. Each data word is then
// added to the accumulator which is then inverted to create
// the checksum. To verify a checksum the accumulator must
// again be cleared and again each value is added. When the
// checksum is added, the output value is compared to zero
// to see if the data sequence was correct.
//
/*********************************************************/

// DEFINES
`define DEL	1		// Clock-to-output delay. Zero
					// time delays can be confusing
					// and sometimes cause problems.
`define BITS 8		// Number of bits in the data word

// TOP MODULE
module Checksum(
		clk,
		reset,
		data,
		out,
		zero);

// INPUTS
input				clk;		// Clock
input				reset;		// Synchronous reset
input [`BITS-1:0]	data;		// Input data

// OUTPUTS
output [`BITS-1:0]	out;		// Checksum output
output 				zero;		// Output is zero?

// INOUTS

// SIGNAL DECLARATIONS
wire				clk;
wire				reset;
wire [`BITS-1:0]	data;
wire [`BITS-1:0]	out;
wire 				zero;
reg  [`BITS-1:0]	acc;		// Accumulator

// PARAMETERS

// ASSIGN STATEMENTS
assign #`DEL zero = (acc == ~`BITS'h0) ? 1'b1 : 1'b0;
assign #`DEL out = ~acc;

// MAIN CODE

// Look at the rising edge of the clock
always @(posedge clk) begin
	if (reset) begin
		// Reset the accumulator
		acc <= #`DEL `BITS'h0;
	end
	else
		acc <= #`DEL acc + data;
end
endmodule		// Checksum