ham_sim.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		Hamming Code simulation
//
// FILE NAME:	ham_sim.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Simulation
//
// DESCRIPTION:	This module provides stimuli for simulating
// single bit error detecting and correcting logic. A
// sequence of data words is generated using a counter. The
// Hamming code bits are appended to the word. For the first
// word, no bits are corrupted. For the second word, bit 1 is
// corrupted, etc. When the most significant bit is
// corrupted, the sequence begins again with no bits
// corrupted. Each time, the data is sent through decoder to
// obtain the correct data. This data is compared to the
// original data, which should match perfectly or an error
// message is displayed and the simulation stops. The
// simulation increments the data word until it wraps back
// around to zero. If this happens and no errors were found,
// the simulation ends successfully.
//
/*********************************************************/

// DEFINES
`define DEL	1		// Clock-to-output delay. Zero
					// time delays can be confusing
					// and sometimes cause problems.
`define BITS 8		// Number of bits in a data word
`define EDC_BITS 4	// Number of EDC bits

// TOP MODULE
module ham_sim();

// INPUTS

// OUTPUTS

// INOUTS

// SIGNAL DECLARATIONS
reg  [`BITS-1:0]		   	data_in;
wire [`EDC_BITS-1:0]	   	edc;
wire [`BITS-1:0]	   	   	data_out;
wire				   	   	error;

wire [`BITS-1:0]	   	   	new_data;	// New data,
										// possibly corrupted
wire [`EDC_BITS-1:0]   	   	new_edc;	// New EDC bits,
										// possibly corrupted
reg					   	   	clock;		// Clock
reg  [`EDC_BITS+`BITS-1:0]	bit_err;  	// Used to force a
						   				// single bit error
reg							start;		// Have we started?

// PARAMETERS

// ASSIGN STATEMENTS
assign #`DEL new_data = data_in ^ bit_err[`BITS-1:0];
assign #`DEL new_edc = edc ^ bit_err[`EDC_BITS+`BITS-1:`BITS];

// MAIN CODE

// Instantiate the EDC generator
HamGen hamgen(
			.data_in(data_in),
			.edc_out(edc));

// Instantiate the EDC decoder
HamDec hamdec(
        .data_in(new_data),
        .edc_in(new_edc),
        .data_out(data_out),
        .error(error));

// Initialize inputs
initial begin
	clock = 1;
	bit_err = 0;
	start = 0;
	data_in = 0;
end

// Generate the clock
always #100 clock = ~clock;

// Simulate

// Look at the rising edge of the clock
always @(posedge clock) begin
	// On the first cycle, corrupt no bits
	// On each subsequent cycle, we corrupt each bit
	// from LSB to MSB
	// We then repeat the process
	if (bit_err)
		bit_err <= #`DEL bit_err << 1;
	else
		bit_err <= #`DEL 1;

	if (data_in == 0) begin
		if (start === 0)
			start <= #`DEL 1;
		else begin
			$display("\nSimulation complete - no errors\n");
			$finish;
		end
	end
	else begin
		if (data_out !== data_in) begin
			$display("\nERROR at time %0t:", $time);
			$display("    data_in = %h", data_in);
			$display("    data_out = %h\n", data_out);

			// Use $stop for debugging
			$stop;
		end
		if ((error !== 1) && (bit_err !== 0)) begin
			$display("\nERROR at time %0t:", $time);
			$display("error signal was not asserted\n");

			// Use $stop for debugging
			$stop;
		end
		else if ((error !== 0) && (bit_err === 0)) begin
			$display("\nERROR at time %0t:", $time);
			$display("error signal was asserted\n");

			// Use $stop for debugging
			$stop;
		end
	end

	// Create the next data input
	data_in <= #`DEL data_in+1;
end
endmodule		// ham_sim