umultiply_sim.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		unsigned integer multiplier simulation
//
// FILE NAME:	umultiply_sim.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Simulation
//
// DESCRIPTION:	This module provides stimuli for simulating
// an unsigned integer multiplier. It generates every
// possible combination of operands and examines each product
// for correctness.
//
/*********************************************************/

// DEFINES
`define OP_BITS 4	// Number of bits in each operand

// TOP MODULE
module umultiply_sim();

// INPUTS

// OUTPUTS

// INOUTS

// SIGNAL DECLARATIONS
reg						clock;
reg						reset;
reg  [`OP_BITS-1:0]		a_in;
reg  [`OP_BITS-1:0]		b_in;
reg						multiply_en;
wire [2*`OP_BITS-1:0]	product_out;
wire					valid;

reg  [2*`OP_BITS:0]		cycle_count;	// Counts valid clock cycles
integer					val_count;	  	// Counts cycles
										// between valid data
reg  [2*`OP_BITS-1:0]	expect;			// Expected output

// PARAMETERS

// ASSIGN STATEMENTS

// MAIN CODE

// Instantiate the multiplier
UnsignedMultiply umult(
			.clk(clock),
			.reset(reset),
			.a(a_in),
			.b(b_in),
			.multiply_en(multiply_en),
			.product(product_out),
			.valid(valid));

// Initialize inputs
initial begin
	clock = 1;
	cycle_count = 0;

	reset = 1;			// Toggle reset to initialize
	#10 reset = 0;		// the valid output

	multiply_en = 1;	// Begin the operation

	val_count = 0;		// How many cycles to output valid data?
end

// Generate the clock
always #100 clock = ~clock;

// Simulate
always @(negedge clock) begin
	if (valid === 1'b1) begin
		// Check the result for correctness
		if (product_out !== expect) begin
			$display("\nERROR at time %0t:", $time);
			$display("Adder is not working");
			if (multiply_en)
				$display("Multiplier is enabled");
			else
				$display("Multiplier is not enabled");
			$display("    a_in = %h", a_in);
			$display("    b_in = %h", b_in);
			$display("    expected result = %h",
						  	expect);
			$display("    actual output = %h\n",
						  	product_out);
		
			// Use $stop for debugging
			$stop;
		end

		// Create inputs between 0 and all 1s
		a_in = cycle_count[2*`OP_BITS-1:`OP_BITS];
		b_in = cycle_count[`OP_BITS-1:0];

		// How many cycles to output valid data?
		val_count = 0;

		// Count the valid cycles
		cycle_count = cycle_count + 1;
		if (cycle_count[2*`OP_BITS]) begin
			// We've cycled once
			case (cycle_count[1:0])
				0: begin
					expect = a_in * b_in;
				end
				1: begin
					multiply_en = 0;	// Stop the operation

					// We changed the inputs, but don't change the
					// previous expected value since we have
					// stopped the operation
				end
				2: begin
					$display("\nSimulation complete - no errors\n");
					$finish;
				end
			endcase
		end
		else begin
			expect = a_in * b_in;
		end
	end
	else begin
		// Keep track of how many cycles to output valid data
		val_count = val_count + 1;

		if (val_count > 2*`OP_BITS+3) begin
			$display("\nERROR at time %0t:", $time);
 			$display("Too many cycles for valid data\n");

			// Use $stop for debugging
			$stop;
		end
	end
end
endmodule		// umultiply_sim