check_sim.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		checksum simulation
//
// FILE NAME:	check_sim.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Simulation
//
// DESCRIPTION:	This module provides stimuli for simulating
// a checksum generator/verifier. First it generates a
// sequence of random data words and records the checksum.
// Then it repeats the sequence of data words with the
// checksum at the end. The checksum output should be zero.
// Then the simulation generates a new sequence of random
// data words and records the checksum. When it repeats
// this sequence with the checksum at the end, it corrupts
// one of the data words. The resulting output should be
// non-zero. It repeats the process for the number of tests
// that are specified.
//
/*********************************************************/

// DEFINES
`define BITS 8			// Number of bits in the data word
`define RBITS `BITS+1	// Used for generating random data
`define LENGTH 512		// Number of data words in the
						// sequence
`define TESTS 16		// Number of tests to perform

// TOP MODULE
module check_sim();

// INPUTS

// OUTPUTS

// INOUTS

// SIGNAL DECLARATIONS
reg					clk;
reg					reset;
reg  [`BITS-1:0]	data;
wire [`BITS-1:0]	out;
wire 				zero;

integer				cycle_count;	// Counts clock cycles
integer				test_count;		// Counts the test number
reg  [`BITS-1:0]	sum;	   		// Save the checksum

// PARAMETERS

// ASSIGN STATEMENTS

// MAIN CODE

// Instantiate the checksum logic
Checksum checksum(
		.clk(clk),
		.reset(reset),
		.data(data),
		.out(out),
		.zero(zero));

// Initialize inputs
initial begin
	clk = 0;
	reset = 1;
	cycle_count = 0;
	test_count = 0;
end

// Generate the clock
always #100 clk = ~clk;

// Simulate
always @(negedge clk) begin
	// Check the zero signal
	if (((out !== `BITS'h0) && (zero !== 1'b0)) ||
		((out === `BITS'h0) && (zero !== 1'b1))) begin
		$display("\nERROR at time %0t:", $time);
		$display("Zero flag is incorrect");
		$display("    checksum = %h", out);
		$display("    zero signal = %b\n", zero);
	
		// Use $stop for debugging
		$stop;
	end

	if (cycle_count !== 0) begin
		// Create random inputs
		data = {$random} % (`RBITS'h1 << `BITS);
	end

	case (cycle_count)
		0:	begin
			// Test checksum
			if (out === ~`BITS'h0)
				$display ("Reset is working");
			else begin
				$display("\nERROR at time %0t:", $time);
				$display("Reset is not working");
				$display("    checksum = %h\n", out);
			
				// Use $stop for debugging
				$stop;
			end
			
			// Deassert the reset signal
			reset = 0;

			// Save the test_count, because the random
			// number generator changes it
			cycle_count = test_count;

		   	// Initialize random number generator
			$random(test_count);

			// Restore the test_count and cycle_count
			test_count = cycle_count;
			cycle_count = 0;

			// Create random inputs
			data = {$random} % (`RBITS'h1 << `BITS);
		end
		`LENGTH: begin
			// Save the checksum
			sum = out;

			// Assert reset
			reset = 1;
		end
		`LENGTH+1: begin
			// Test checksum
			if (out === ~`BITS'h0)
				$display ("Reset is working");
			else begin
				$display("\nERROR at time %0t:", $time);
				$display("Reset is not working");
				$display("    checksum = %h\n", out);
			
				// Use $stop for debugging
				$stop;
			end
			
			// Deassert the reset signal
			reset = 0;

			// Save the test_count, because the random
			// number generator changes it
			cycle_count = test_count;

		   	// Initialize random number generator
			$random(test_count);

			// Restore the test_count and cycle_count
			test_count = cycle_count;
			cycle_count = `LENGTH+1;

			// Create random inputs
			data = {$random} % (`RBITS'h1 << `BITS);
		end
		`LENGTH+2: begin
			if (test_count & 1) begin
				$display("Corrupting data word");
				// Corrupt one bit of one data word
				data = data ^ `BITS'h1;
			end
		end
		2*`LENGTH+1: begin
			// Use the checksum as the last data word
			data = sum;
		end
		2*`LENGTH+2: begin
			// Test outputs
			if (test_count & 1) begin
				if ((out !== `BITS'h0) && (zero !== 1'b1))
					$display ("Checksum test #%d passed",
						test_count);
				else begin
					$display("\nERROR at time %0t:", $time);
					$display("Checksum is incorrect");
					$display("    zero flag      = %h", zero);
					$display("    checksum       = %h", out);
					$display("    expected value = non-zero\n");
				
					// Use $stop for debugging
					$stop;
				end
			end
			else begin
				if ((out === `BITS'h0) && (zero === 1'b1))
					$display ("Checksum test #%d passed",
						test_count);
				else begin
					$display("\nERROR at time %0t:", $time);
					$display("Checksum is incorrect");
					$display("    zero flag      = %h", zero);
					$display("    checksum       = %h", out);
					$display("    expected value = %h\n",
						`BITS'h0);
				
					// Use $stop for debugging
					$stop;
				end
			end

			// Increment the test count
			test_count = test_count + 1;
			if (test_count === `TESTS) begin
				$display("\nSimulation complete - no errors\n");
				$finish;
			end

			// Initialize cycle_count so that it is
			// zero after incrementaion
			cycle_count = -1;

			// Assert the reset signal
			reset = 1;

		end
	endcase
	// Increment the cycle count
	cycle_count = cycle_count + 1;
end
endmodule		// check_sim