encr_sim.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		encrypter/decrypter simulation
//
// FILE NAME:	encr_sim.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Simulation
//
// DESCRIPTION:	This module provides stimuli for simulating
// a data encrypter/decrypter. It generates a random sequence
// of data words and a random encryption key. It uses the key
// to encrypt the sequence and store the encrypted data. Then
// it uses the key to decrypt the data and confirms that the
// decrypted data matches the original data.
//
/*********************************************************/

// DEFINES
`define DEL	1		// Clock-to-output delay. Zero
					// time delays can be confusing
					// and sometimes cause problems.

`define WORD_SZ 8	// Number of bits in a data word
`define SEQ_LEN 100	// Number of words to encrypt

// TOP MODULE
module encr_sim();

// INPUTS

// OUTPUTS

// INOUTS

// SIGNAL DECLARATIONS
reg					clock;
reg					load;
reg  [`WORD_SZ-1:0]	data_in;
reg  [`WORD_SZ-1:0]	key;
wire [`WORD_SZ-1:0]	data_out;

reg  [`WORD_SZ-1:0]	data_exp;		// Expected data output
									// Data memory
reg	 [`WORD_SZ-1:0]	data_mem[0:`SEQ_LEN-1];
integer				index;			// Index into data memory
							
reg					encrypt_flag;	// Are we encrypting
							   		// or decrypting?

// PARAMETERS

// ASSIGN STATEMENTS

// MAIN CODE

// Instantiate the encrypter
Encrypt encrypt(
	   	.clk(clock),
	   	.load(load),
		.key(key),
		.data_in(data_in),
		.data_out(data_out));

// Initialize inputs
initial begin
	clock = 0;
	load = 1;			// Load the key
	index = 0;
	encrypt_flag = 1;	// Encrypting

	$random(0);	   		// Initialize random number generator
	key = {$random} % (`WORD_SZ'h0 - `WORD_SZ'h1);

end

// Generate the clock
always #100 clock = ~clock;

// Simulate
always @(negedge clock) begin
	if (index === 1) begin
		// Stop loading the key
		load = 0;
	end

	if (encrypt_flag) begin
		// Input random data for encryption
		data_in = {$random} % (`WORD_SZ'h0 - `WORD_SZ'h1);

		// Wait for the outputs to settle
		#`DEL;
		#`DEL;
		#`DEL;

		// Save the encrypted output data for later
		data_mem[index] = data_out;

		// Is is the end of the sequence?
		if (index === `SEQ_LEN-1) begin
			// Start over and begin decrypting
			index = 0;
			encrypt_flag = 0;

			$random(0);			// Initialize random number generator
			load = 1;	// Reload the key into the circuit
			key = {$random} % (`WORD_SZ'h0 - `WORD_SZ'h1);
		end
		else begin
			// Increment the index
			index = index + 1;
		end
	end
	else begin
		// Decrypt the encrypted data
		data_in = data_mem[index];

		// Wait for the outputs to settle
		#`DEL;
		#`DEL;
		#`DEL;

		// Get the expected data
		data_exp = {$random} % (`WORD_SZ'h0 - `WORD_SZ'h1);

		// Check the output
		if (data_exp !== data_out) begin
			$display("\nERROR at time %0t:", $time);
			$display("Encryption/decryption not working");
			$display("    expected data = %h", data_exp);
			$display("    actual data   = %h\n", data_out);
		
			// Use $stop for debugging
			$stop;
		end

		// Is it the end of the sequence?
		if (index === `SEQ_LEN-1) begin
			$display("\nSimulation complete - no errors\n");
			$finish;
		end
		else begin
			// Increment the index
			index = index + 1;
		end
	end
end
endmodule		// encr_sim