crc_sim.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		CRC simulation
//
// FILE NAME:	crc_sim.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Simulation
//
// DESCRIPTION:	This module provides stimuli for simulating
// a CRC generator/verifier. It creates a large, random,
// frame of data which is shifted through an LFSR to produce
// an FCS which is appended to the frame. In every even
// frame, a single bit is corrupted. Each frame, with the
// appended FCS, is then shifted through the LFSR again. For
// uncorrupted frames, the LFSR is expected to contain zero
// at the end. For corrupted frames, the LFSR is expected to
// have a non-zero value.
//
/*********************************************************/

// DEFINES
`define FCS 8		   			// Number of bits in the fcs
`define FRAME 128				// Number of bytes in the frame
`define BFRAME `FRAME*8			// Number of bits in the frame
`define TOT_BITS `BFRAME+`FCS	// Total number of bits
								// including frame and FCS
`define FRAME_CNT 16			// Number of frames to test

// TOP MODULE
module crc_sim();

// INPUTS

// OUTPUTS

// INOUTS

// SIGNAL DECLARATIONS
reg					   	clk;
reg					   	reset;
wire				   	bit_in;
wire [`FCS-1:0]			fcs;

integer				   	cycle_count;	// Counts clock cycles
integer				   	frame_count;	// Counts frames
reg  [`TOT_BITS-1:0]	frame_data;		// Frame data bits
reg					   	gen_check;		// Generate/check CRC
					   					// = 1 to generate CRC
					   					// = 0 to check CRC
integer					i;				// Temporary variable

// PARAMETERS

// ASSIGN STATEMENTS
assign bit_in = frame_data[cycle_count];

// MAIN CODE

// Instantiate the CRC logic
CRC crc(
		.clk(clk),
		.reset(reset),
		.bit_in(bit_in),
		.fcs(fcs));

// Initialize inputs
initial begin
	clk = 0;
	reset = 1;					// Reset the FCS
	gen_check = 1;				// Generate FCS
	cycle_count = `TOT_BITS - 1;
	frame_count = `FRAME_CNT;

	// Initialize random number generator
	$random(0);

	// Create random frame data of `FRAME bytes
	for (i = 0; i < `FRAME; i = i + 1) begin
		frame_data = (frame_data << 8) | ({$random} % 256);
	end
	// Then shift it left `FCS places
	frame_data = frame_data << `FCS;
end

// Generate the clock
always #100 clk = ~clk;

// Simulate
always @(negedge clk) begin
	// If reset is on, turn it off
	if (reset)
		reset = 0;
	else begin
		if (cycle_count === 0) begin
			if (gen_check) begin
				// Begin the CRC check
				gen_check = 0;
				cycle_count = `TOT_BITS - 1;

				// Put the FCS at the end of the data stream
				frame_data[`FCS-1:0] = fcs;

				// Corrupt one bit one every other test
				if ((frame_count & 1) === 0) begin
					$display("Corrupting frame");

					// Choose a random bit to corrupt
					i = {$random} % (`TOT_BITS);
					frame_data = frame_data ^ (`TOT_BITS'h1 << i);
				end

				// Reset the FCS
				reset = 1;
			end
			else begin
				if (((frame_count & 1) !== 0) && 
					(fcs !== `FCS'h0)) begin
					$display("\nERROR at time %0t:", $time);
					$display("CRC produced %h instead of 0\n", fcs, );
					
					// Use $stop for debugging
					$stop;
				end
				else if (((frame_count & 1) === 0) && 
					(fcs === `FCS'h0)) begin
					$display("\nERROR at time %0t:", $time);
					$display("CRC passed a bad frame\n", fcs, );
				
					// Use $stop for debugging
					$stop;
				end
				else begin
					$display("CRC #%d passed",
						`FRAME_CNT-frame_count);

					// Reset the FCS
					reset = 1;
				end

				if (frame_count === 0) begin
					$display("\nSimulation complete - no errors\n");
					$finish;
				end
				else begin
					// Start the next frame
					frame_count = frame_count - 1;
					cycle_count = `TOT_BITS - 1;
					gen_check = 1;

					// Create random frame data of `FRAME bytes
					for (i = 0; i < `FRAME; i = i + 1) begin
						frame_data = (frame_data << 8) |
							({$random} % 256);
					end
					// Then shift it left `FCS places
					frame_data = frame_data << `FCS;
				end
			end
		end
		// Decrement the cycle count
		cycle_count = cycle_count - 1;
	end
end
endmodule		// crc_sim