par.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		parity generator/checker
//
// FILE NAME:	par.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Behavioral and RTL
//
// DESCRIPTION:	This module defines an parity generator
// and checker. Each bit of parity corresponds to a byte
// of input data.
//
/*********************************************************/

// DEFINES
`define DEL	1		// Clock-to-output delay. Zero
					// time delays can be confusing
					// and sometimes cause problems.

// TOP MODULE
module Parity(
		data,
		par_in,
		even_odd,
		par_out,
		error);

// INPUTS
input [31:0]	data;		// 32-bit data input
input [3:0]		par_in;		// Parity input
input			even_odd;	// Select even or odd parity

// OUTPUTS
output [3:0]	par_out;	// Parity output
output [3:0]	error;		// Error output

// INOUTS

// SIGNAL DECLARATIONS
wire [31:0]		data;
wire [3:0]		par_in;
wire			even_odd;
wire [3:0]		par_out;
wire [3:0]		error;

// PARAMETERS

// ASSIGN STATEMENTS
assign #`DEL par_out[3] = even_odd ? ^data[31:24] :
						~^data[31:24];
assign #`DEL par_out[2] = even_odd ? ^data[23:16] :
						~^data[23:16];
assign #`DEL par_out[1] = even_odd ? ^data[15:8] :
						~^data[15:8];
assign #`DEL par_out[0] = even_odd ? ^data[7:0] :
						~^data[7:0];

assign #`DEL error[3] = even_odd ? ^{data[31:24], par_in[3]} :
						~^{data[31:24], par_in[3]};
assign #`DEL error[2] = even_odd ? ^{data[23:16], par_in[2]} :
						~^{data[23:16], par_in[2]};
assign #`DEL error[1] = even_odd ? ^{data[15:8], par_in[1]} :
						~^{data[15:8], par_in[1]};
assign #`DEL error[0] = even_odd ? ^{data[7:0], par_in[0]} :
						~^{data[7:0], par_in[0]};

// MAIN CODE

endmodule		// Parity