ram_sim.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		RAM simulation
//
// FILE NAME:	ram_sim.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Simulation
//
// DESCRIPTION:	This module provides stimuli for simulating
// a Random Access Memory. It writes unique values to each
// location then reads each location back and checks for
// correctness.
//
/*********************************************************/

// DEFINES
`define DEL	1			// Clock-to-output delay. Zero
						// time delays can be confusing
						// and sometimes cause problems.

`define RAM_WIDTH 8		// Width of RAM (number of bits)
`define RAM_DEPTH 16	// Depth of RAM (number of bytes)
`define ADDR_SZ 4		// Number of bits required to
						// represent the RAM address

// TOP MODULE
module ram_sim();

// INPUTS

// OUTPUTS

// INOUTS

// SIGNAL DECLARATIONS
reg  [`ADDR_SZ-1:0] 	address;
reg 					write_n;
reg 					oe_n;
wire [`RAM_WIDTH-1:0]	data;

reg  [`RAM_WIDTH-1:0]	data_in;	// Input data
reg  [`RAM_WIDTH-1:0]	data_exp;	// Expected output data

// PARAMETERS

// ASSIGN STATEMENTS
assign #`DEL data = oe_n ? data_in : `RAM_WIDTH'bz;

// MAIN CODE

// Instantiate the counter
Ram ram(
		.data(data),
		.address(address),
		.write_n(write_n),
		.oe_n(oe_n));

// Initialize inputs
initial begin
	data_in = 0;
	address = 0;
	write_n = 1;
	oe_n = 1;

	// Start the action
	write_n <= #20 0;
end

// Simulate
// Write the RAM
always @(negedge write_n) begin
	// Bring write high to write to the RAM
	#10 write_n = 1;

	// Set up the address for the next write
	#10 address = address + 1;

	if (address === 0) begin
		// If the address is 0, we've written the entire RAM
		// Set up the reads
		oe_n <= #10 0;

		data_exp = 0;
	end
	else begin
		// Otherwise set up the data for the next write
		// We decrement data while incrementing address
		// so that we know we are writing the data, not 
		// the address into memory
		data_in <= #10 data_in - 1;

		write_n <= #10 0;
	end
end

// Read the RAM
always @(negedge oe_n) begin
	// Read the data and compare
	#`DEL;
	#`DEL;
	if (data !== data_exp) begin
		$display("\nERROR at time %0t:", $time);
		$display("    Data read     = %h", data);
		$display("    Data expected = %h\n", data_exp);
				
		// Use $stop for debugging
		$stop;
	end
	
	// Increment the address
	#10 address = address + 1;
	if (address === 0) begin
		// If the address is 0, we've read the entire RAM
		$display("\nSimulation complete - no errors\n");
		$finish;
	end

	// Decrement the expected data
	data_exp <= #10 data_exp - 1;

	// Set up the next rising edge of output enable
	oe_n <= #10 1;
	// Set up the next falling edge of output enable
	oe_n <= #30 0;
end
endmodule		// ram_sim