add_sim.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		adder simulation
//
// FILE NAME:	add_sim.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Simulation
//
// DESCRIPTION:	This module provides stimuli for simulating
// an adder. The synchronous reset is first checked. Then,
// randomly generated operands are added together and the
// output is compared to the expected sum and carry out.
//
/*********************************************************/

// DEFINES
`define TEST_NUM 255	// Number of addition operations
						// to test
`define BITS 32			// Bit width of the operands
`define EBITS `BITS+1	// Bit width of data plus carry bit

// TOP MODULE
module add_sim();

// INPUTS

// OUTPUTS

// INOUTS

// SIGNAL DECLARATIONS
reg					clock;
reg					reset_n;
reg					add_en;
reg  [`BITS-1:0]	a_in;
reg  [`BITS-1:0]	b_in;
wire [`BITS-1:0]	sum_out;
wire				overflow;
wire				valid;

integer				cycle_count;	// Counts valid clock cycles
integer				val_count;	  	// Counts cycles between
									// valid data
reg  [`EBITS-1:0]	expect;			// Expected adder output

// PARAMETERS

// ASSIGN STATEMENTS

// MAIN CODE

// Instantiate the adder
Adder adder1(
			.clk(clock),
			.a(a_in),
			.b(b_in),
			.reset_n(reset_n),
			.add_en(add_en),
			.out(sum_out),
			.cout(overflow),
			.valid(valid));

// Initialize inputs
initial begin
	clock = 0;
	reset_n = 0;
	add_en = 1;
	cycle_count = 0;
	val_count = 0;
	$random(0);	   	// Initialize random number generator
end

// Generate the clock
always #100 clock = ~clock;

// Simulate
always @(negedge clock) begin
	if (valid === 1'b1) begin
		case (cycle_count)
			0:	begin
				// Test outputs
				if ((sum_out === `BITS'h00000000) &&
						(overflow === 1'b0))
					$display ("Reset is working");
				else begin
					$display("\nERROR at time %0t:", $time);
					$display("Reset is not working");
					$display("    sum_out = %h", sum_out);
					$display("    overflow = %b\n", overflow);
				
					// Use $stop for debugging
					$stop;
				end
				// Test valid output signal
				if (valid === 1'b1)
					$display ("Valid signal is working");
				else begin
					$display("\nERROR at time %0t:", $time);
					$display("Valid signal is not working");
					$display("    valid = %b\n", valid);
				
					// Use $stop for debugging
					$stop;
				end
			
				// Deassert the reset signal
				reset_n = 1;

				// Create random inputs
				// between 0 and all 1s
				a_in = {$random} % (`EBITS'h1 << `BITS);
				b_in = {$random} % (`EBITS'h1 << `BITS);
				expect = a_in + b_in;

				// Don't begin the add operation just yet
				add_en = 0;

				// How many cycles to output valid data?
				val_count = 0;
			end
			1:	begin
				// This should be the very next clock cycle
				if (val_count !== 1'b0) begin
					$display("\nERROR at time %0t:", $time);
					$display("Valid is not held after reset\n");
				
					// Use $stop for debugging
					$stop;
				end

				// Test outputs
				if ((sum_out === `BITS'h00000000) &&
						(overflow === 1'b0))
					$display ("Reset is working");
				else begin
					$display("\nERROR at time %0t:", $time);
					$display("Reset is not working");
					$display("    sum_out = %h", sum_out);
					$display("    overflow = %b\n", overflow);
				
					// Use $stop for debugging
					$stop;
				end
				// Test valid output signal
				if (valid === 1'b1)
					$display ("Valid signal is working");
				else begin
					$display("\nERROR at time %0t:", $time);
					$display("Valid signal is not working");
					$display("    valid = %b\n", valid);
				
					// Use $stop for debugging
					$stop;
				end
			
				// Begin the add operation
				add_en = 1;

				// How many cycles to output valid data?
				val_count = 0;
			end
			`TEST_NUM+1: begin
				// Check the result for correctness
				if ({overflow, sum_out} !== expect) begin
					$display("\nERROR at time %0t:", $time);
					$display("Adder is not working");
					$display("    a_in = %h", a_in);
					$display("    b_in = %h", b_in);
					$display("    expected result = %h",
								  	expect);
					$display("    actual output = %h\n",
								  	{overflow, sum_out});
				
					// Use $stop for debugging
					$stop;
				end

				// Create random inputs
				// between 0 and all 1s
				a_in = {$random} % (`EBITS'h1 << `BITS);
				b_in = {$random} % (`EBITS'h1 << `BITS);

				// Do not change the expected value
				// since we will  be disabling addition
				add_en = 0;

				// How many cycles to output valid data?
				val_count = 0;
			end
			`TEST_NUM+2:	begin
				// This should be the very next clock cycle
				if (val_count !== 0) begin
					$display("\nERROR at time %0t:", $time);
					$display("Valid is not held\n");
				
					// Use $stop for debugging
					$stop;
				end
				// Check the result for correctness
				if ({overflow, sum_out} !== expect) begin
					$display("\nERROR at time %0t:", $time);
					$display("Adder is not working");
					$display("    a_in = %h", a_in);
					$display("    b_in = %h", b_in);
					$display("    expected result = %h", expect);
					$display("    actual output = %h\n",
								  	{overflow, sum_out});
				
					// Use $stop for debugging
					$stop;
				end

				$display("\nSimulation complete - no errors\n");
				$finish;
			end
			default: begin
				// Check the result for correctness
				if ({overflow, sum_out} !== expect) begin
					$display("\nERROR at time %0t:", $time);
					$display("Adder is not working");
					$display("    a_in = %h", a_in);
					$display("    b_in = %h", b_in);
					$display("    expected result = %h",
								  	expect);
					$display("    actual output = %h\n",
								  	{overflow, sum_out});
				
					// Use $stop for debugging
					$stop;
				end

				// Create random inputs
				// between 0 and all 1s
				a_in = {$random} % (`EBITS'h1 << `BITS);
				b_in = {$random} % (`EBITS'h1 << `BITS);
				expect = a_in + b_in;

				// Begin the add operation
				add_en = 1;

				// How many cycles to output valid data?
				val_count = 0;
			end
		endcase

		// Count the valid cycles
		cycle_count = cycle_count + 1;
	end
	else begin
		// Keep track of how many cycles to output valid data
		val_count = val_count + 1;

		if (val_count > 11) begin
			$display("\nERROR at time %0t:", $time);
 			$display("Too many cycles for valid data\n");

			// Use $stop for debugging
			$stop;
		end
	end
end
endmodule		// add_sim