cnt_sim.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		counter simulation
//
// FILE NAME:	cnt_sim.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Simulation
//
// DESCRIPTION:	This module provides stimuli for simulating
// an up/down counter. It tests the asynchronous reset and
// preset controls and the synchronous load control. It loads
// a value and counts up until the counter overflows. It then
// loads a new value and counts down until the counter
// overflows. During each cycle, the output is compared to
// the expected output.
//
/*********************************************************/

// DEFINES
`define DEL	1				// Clock-to-output delay. Zero
							// time delays can be confusing
							// and sometimes cause problems.
`define BITS 8				// Number of bits in counter

`define PATTERN1 `BITS'h1 	// Starting data for counting up
`define PATTERN2 `BITS'h3 	// Starting data for counting down

// TOP MODULE
module cnt_sim();

// INPUTS

// OUTPUTS

// INOUTS

// SIGNAL DECLARATIONS
reg					clock;
reg					reset_n;
reg					preset_n;
reg					load;
reg					up_down;
reg					count_en;
reg  [`BITS-1:0]	data_in;
wire [`BITS-1:0]	data_out;
wire				overflow;

reg  [`BITS-1:0]	cycle_count;	// Cycle count variable
integer				test_part;		// Which part of the test
									// are we doing?
reg  [`BITS-1:0]	count_test;		// Used to compare against
									// the counter output
reg  				carry_test;		// Used to compare against
									// the carry output

// PARAMETERS

// ASSIGN STATEMENTS

// MAIN CODE

// Instantiate the counter
Counter counter1(
			.clk(clock),
			.in(data_in),
			.reset_n(reset_n),
			.preset_n(preset_n),
			.load(load),
			.up_down(up_down),
			.count_en(count_en),
			.out(data_out),
			.carry_out(overflow));

// Initialize inputs
initial begin
	clock = 1;
	reset_n = 1;
	preset_n = 1;
	load = 0;
	count_en = 0;
	cycle_count = `BITS'b0;
	test_part = 0;			// We are doing the first part
							// of the test
end

// Generate the clock
always #100 clock = ~clock;

// Simulate
always @(negedge clock) begin
	case (test_part)
		0: begin
			case (cycle_count)
				`BITS'h0:	begin
					// Assert the reset signal
					reset_n = 0;
					
					// Wait for the outputs to change
					// asynchronously
					#`DEL
					#`DEL
					// Test outputs
					if (data_out === `BITS'h0)
						$display ("Reset is working");
					else begin
						$display("\nERROR at time %0t:", $time);
						$display("Reset is not working");
						$display("    data_out = %h\n", data_out);
						
						// Use $stop for debugging
						$stop;
					end

					// Deassert the reset signal
					reset_n = 1;

					// Set the expected outputs
					count_test = `BITS'h0;
					carry_test = 1'bx;
				end
				`BITS'h1:	begin
					// Assert the preset signal
					preset_n = 0;
					
					// Wait for the outputs to change
					// asynchronously
					#`DEL
					#`DEL
					// Test outputs
					if (data_out === ~`BITS'h0)
						$display ("Preset is working");
					else begin
						$display("\nERROR at time %0t:", $time);
						$display("Preset is not working");
						$display("    data_out = %h\n", data_out);
						
						// Use $stop for debugging
						$stop;
					end

					// Deassert the preset signal
					preset_n = 1;

					// Set the expected outputs
					count_test = ~`BITS'h0;
				end
				`BITS'h2:	begin
					// Load data into the counter
					data_in = `PATTERN1;
					load = 1'b1;
				end
				`BITS'h3:	begin
					// Test outputs
					if (data_out === `PATTERN1)
						$display ("Load is working");
					else begin
						$display("\nERROR at time %0t:", $time);
						$display("Load is not working");
						$display("    expected data_out = %h",
									`PATTERN1);
						$display("    actual   data_out = %h\n",
									data_out);
						
						// Use $stop for debugging
						$stop;
					end

					// Deassert the load enable signal
					load = 1'b0;

					// Set the expected outputs
					count_test = `PATTERN1;
				end
				`BITS'h4:	begin
					// Test outputs to see that data was not lost
					if (data_out === `PATTERN1)
						$display ("Counter hold is working");
					else begin
						$display("\nERROR at time %0t:", $time);
						$display("Counter hold is not working");
						$display("    expected data_out = %h",
									`PATTERN1);
						$display("    actual   data_out = %h\n",
									data_out);
						
						// Use $stop for debugging
						$stop;
					end

					// Count up
					count_en = 1'b1;
					up_down = 1;

					// Set the expected outputs
					count_test = `PATTERN1;
					carry_test = 1'b0;
				end
				~`BITS'h0:	begin
					// Start the second part of the test
					test_part = 1;
				end
			endcase
		end
		1: begin
			case (cycle_count)
				`BITS'h4:	begin
					// Load data into the counter
					data_in = `PATTERN2;
					count_test = `PATTERN2;
					load = 1'b1;

					// Set the expected outputs
					count_test = `PATTERN1;
				end
				`BITS'h5:	begin
					// Test outputs
					if (data_out === `PATTERN2)
						$display ("Load is working");
					else begin
						$display("\nERROR at time %0t:", $time);
						$display("Load is not working");
						$display("    expected data_out = %h",
										`PATTERN2);
						$display("    actual   data_out = %h\n",
										data_out);
						
						// Use $stop for debugging
						$stop;
					end

					// Count down
					count_en = 1'b1;
					up_down = 1'b0;
					load = 1'b0;

					// Set the expected outputs
					count_test = `PATTERN2;
				end
				~`BITS'h0:	begin
					// Start the third part of the test
					test_part = 2;
				end
			endcase
		end
		2: begin
			case (cycle_count)
				`BITS'h5:	begin
					$display("\nSimulation complete - no errors\n");
					$finish;
				end
			endcase
		end
	endcase

	// Test the counter output
	if (data_out !== count_test) begin
		$display("\nERROR at time %0t:", $time);
		$display("Count is incorrect");
		$display("    expected output = %h", count_test);
		$display("    actual   output = %h\n", data_out);
				
		// Use $stop for debugging
		$stop;
	end

		// Test the overflow if we are counting
		if ((count_en) && (overflow !== carry_test)) begin
		$display("\nERROR at time %0t:", $time);
		$display("Carry out is incorrect");
		$display("    expected carry = %h", carry_test);
		$display("    actual   carry = %h\n", overflow);
				
		// Use $stop for debugging
		$stop;
	end

	// Determine the expected outputs for the next cycle
	if (up_down === 1'b1) begin
		if (count_en === 1'b1)
			count_test = count_test + `BITS'h1;
		if (count_test === ~`BITS'h0)
			carry_test = 1'b1;
		else
			carry_test = 1'b0;
	end
	else if (up_down === 1'b0) begin
		if (count_en === 1'b1)
			count_test = count_test - `BITS'h1;
		if (count_test === `BITS'h0)
			carry_test = 1'b1;
		else
			carry_test = 1'b0;
	end

	// Increment the cycle counter
	cycle_count = cycle_count + 1;
end
endmodule		// cnt_sim