fullcase1.v

各种基本单元的verilog模块.对初学者很有帮助的.

/*********************************************************/
// MODULE:		Full case example
//
// FILE NAME:	fullcase1.v
// VERSION:		1.0
// DATE:		January 1, 1999
// AUTHOR:		Bob Zeidman, Zeidman Consulting
// 
// CODE TYPE:	Register Transfer Level
//
// DESCRIPTION:	This module defines a state machine. All
// of the states are defined, resulting in no latches when
// synthesized.
//
/*********************************************************/

// DEFINES

// TOP MODULE
module	StateMachine(
		out,
		clk);

// INPUTS
input			clk;		// Clock

// OUTPUTS
output			out;		// Output

// INOUTS

// SIGNAL DECLARATIONS
wire			clk;
wire			out;
reg  [1:0]		state;		// Current state
reg  [1:0]		newstate;  	// New state after clock

// PARAMETERS

// ASSIGN STATEMENTS
assign out = &state;

// MAIN CODE

// Prepare the next state
always @(state) begin
	case (state)
		2'b00:	newstate <= 3'b01;
		2'b01:	newstate <= 3'b11;
		2'b11:	newstate <= 3'b00;
		default: newstate <= 3'bx;
	endcase
end

// Look at the rising edge of clock for state transitions
always @(posedge clk) begin
	state <= newstate;
end
endmodule		// StateMachine