com.v

verilog 实现 优化的16位比较器 可以输出大于

// ******************************************************************
// ** Revision     : 1.0
// ** File name    : com.v
// ** Module name  : COMP16 
// ** Discription  : module COMP16 is a 16-bit comparetors,COMP1 is a one bit comparators ,LEVEL is a contorl module,
//                   2 COMP1 and 1 LEVEL construct a COMP2,similarly COMP4,COMP8,COMP16
// ** Ps           : 
// ** Simulator    : Modlesim SE PLUS V5.6/Verilog Pro6.5
// ** Synthesizer  : 
// ** Author       : GHT
// ** Modify       : 
// *******************************************************************
`timescale 1ns/100ps

module COMP1(O,S,A,B);   //1 bit comparators
output O;                //O: output,result of comparision
output S;                //S: control signal C=1: A==B  C=0:  A!=B
input  A;                //1 bit input A
input  B;                //1 bit input B
wire   O,S,A,B;
wire   t;                // inside wire t=~B
not(t,B);
and(O,A,t);
xnor(S,A,B); 
endmodule

module LEVEL(O,S,I1_o,I1_s,I0_o,I0_s);  //
output O;
output S;
input  I1_o;
input  I1_s;
input  I0_o;
input  I0_s;
wire   O,S,I1_o,I1_s,I0_o,I0,s; 
wire   t;                      //inside wire
and(t,I1_s,I0_o);
and(S,I1_s,I0_s);
or(O,I1_o,t);
endmodule

module COMP2(O,S,A,B);   //2 bit comparators 
output O;
output S;
input  [1:0] A;
input  [1:0] B;
wire   O,S;
wire   [1:0] A,B;
wire   c1_o,c1_s,c0_o,c0_s;  //inside wire
COMP1 c1(c1_o,c1_s,A[1],B[1]),c0(c0_o,c0_s,A[0],B[0]);
LEVEL l1(O,S,c1_o,c1_s,c0_o,c0_s);
endmodule       
       
module COMP4(O,S,A,B);   //4 bit comparators 
output O;
output S;
input  [3:0] A;
input  [3:0] B;
wire   O,S;
wire   [3:0] A,B;
wire   c1_o,c1_s,c0_o,c0_s;  //inside wire
COMP2 c1(c1_o,c1_s,A[3:2],B[3:2]),c0(c0_o,c0_s,A[1:0],B[1:0]);
LEVEL l1(O,S,c1_o,c1_s,c0_o,c0_s);
endmodule   
       
module COMP8(O,S,A,B);   //8 bit comparators 
output O;
output S;
input  [7:0] A;
input  [7:0] B;
wire   O,S;
wire   [7:0] A,B;
wire   c1_o,c1_s,c0_o,c0_s;  //inside wire
COMP4 c1(c1_o,c1_s,A[7:4],B[7:4]),c0(c0_o,c0_s,A[3:0],B[3:0]);
LEVEL l1(O,S,c1_o,c1_s,c0_o,c0_s);
endmodule      

module COMP16(O,S,A,B);   //16 bit comparators 
output O;
output S;
input  [15:0] A;
input  [15:0] B;
wire   O,S;
wire   [15:0] A,B;
wire   c1_o,c1_s,c0_o,c0_s;  //inside wire
COMP8 c1(c1_o,c1_s,A[15:8],B[15:8]),c0(c0_o,c0_s,A[7:0],B[7:0]);
LEVEL l1(O,S,c1_o,c1_s,c0_o,c0_s);
endmodule