📄 system_stm32f10x.lst
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186 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
187 #ifndef STM32F10X_CL
188 RCC->CFGR &= (uint32_t)0xF8FF0000;
189 #else
190 RCC->CFGR &= (uint32_t)0xF0FF0000;
\ 0000000E .... LDR.N R0,??DataTable2_1 ;; 0x40021004
\ 00000010 0068 LDR R0,[R0, #+0]
\ 00000012 .... LDR.N R1,??DataTable2_2 ;; 0xf0ff0000
\ 00000014 0840 ANDS R0,R1,R0
\ 00000016 .... LDR.N R1,??DataTable2_1 ;; 0x40021004
\ 00000018 0860 STR R0,[R1, #+0]
191 #endif /* STM32F10X_CL */
192
193 /* Reset HSEON, CSSON and PLLON bits */
194 RCC->CR &= (uint32_t)0xFEF6FFFF;
\ 0000001A .... LDR.N R0,??DataTable2 ;; 0x40021000
\ 0000001C 0068 LDR R0,[R0, #+0]
\ 0000001E .... LDR.N R1,??DataTable2_3 ;; 0xfef6ffff
\ 00000020 0840 ANDS R0,R1,R0
\ 00000022 .... LDR.N R1,??DataTable2 ;; 0x40021000
\ 00000024 0860 STR R0,[R1, #+0]
195
196 /* Reset HSEBYP bit */
197 RCC->CR &= (uint32_t)0xFFFBFFFF;
\ 00000026 .... LDR.N R0,??DataTable2 ;; 0x40021000
\ 00000028 0068 LDR R0,[R0, #+0]
\ 0000002A 30F48020 BICS R0,R0,#0x40000
\ 0000002E .... LDR.N R1,??DataTable2 ;; 0x40021000
\ 00000030 0860 STR R0,[R1, #+0]
198
199 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
200 RCC->CFGR &= (uint32_t)0xFF80FFFF;
\ 00000032 .... LDR.N R0,??DataTable2_1 ;; 0x40021004
\ 00000034 0068 LDR R0,[R0, #+0]
\ 00000036 30F4FE00 BICS R0,R0,#0x7F0000
\ 0000003A .... LDR.N R1,??DataTable2_1 ;; 0x40021004
\ 0000003C 0860 STR R0,[R1, #+0]
201
202 #ifdef STM32F10X_CL
203 /* Reset PLL2ON and PLL3ON bits */
204 RCC->CR &= (uint32_t)0xEBFFFFFF;
\ 0000003E .... LDR.N R0,??DataTable2 ;; 0x40021000
\ 00000040 0068 LDR R0,[R0, #+0]
\ 00000042 30F0A050 BICS R0,R0,#0x14000000
\ 00000046 .... LDR.N R1,??DataTable2 ;; 0x40021000
\ 00000048 0860 STR R0,[R1, #+0]
205
206 /* Disable all interrupts and clear pending bits */
207 RCC->CIR = 0x00FF0000;
\ 0000004A .... LDR.N R0,??DataTable2_4 ;; 0x40021008
\ 0000004C 5FF47F01 MOVS R1,#+16711680
\ 00000050 0160 STR R1,[R0, #+0]
208
209 /* Reset CFGR2 register */
210 RCC->CFGR2 = 0x00000000;
\ 00000052 .... LDR.N R0,??DataTable2_5 ;; 0x4002102c
\ 00000054 0021 MOVS R1,#+0
\ 00000056 0160 STR R1,[R0, #+0]
211 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
212 /* Disable all interrupts and clear pending bits */
213 RCC->CIR = 0x009F0000;
214
215 /* Reset CFGR2 register */
216 RCC->CFGR2 = 0x00000000;
217 #else
218 /* Disable all interrupts and clear pending bits */
219 RCC->CIR = 0x009F0000;
220 #endif /* STM32F10X_CL */
221
222 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
223 #ifdef DATA_IN_ExtSRAM
224 SystemInit_ExtMemCtl();
225 #endif /* DATA_IN_ExtSRAM */
226 #endif
227
228 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
229 /* Configure the Flash Latency cycles and enable prefetch buffer */
230 SetSysClock();
\ 00000058 ........ BL SetSysClock
231
232 #ifdef VECT_TAB_SRAM
233 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
234 #else
235 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
\ 0000005C .... LDR.N R0,??DataTable2_6 ;; 0xe000ed08
\ 0000005E 5FF00061 MOVS R1,#+134217728
\ 00000062 0160 STR R1,[R0, #+0]
236 #endif
237 }
\ 00000064 01BD POP {R0,PC} ;; return
238
239 /**
240 * @brief Update SystemCoreClock according to Clock Register Values
241 * @note None
242 * @param None
243 * @retval None
244 */
\ In section .text, align 2, keep-with-next
245 void SystemCoreClockUpdate (void)
246 {
\ SystemCoreClockUpdate:
\ 00000000 F0B4 PUSH {R4-R7}
247 uint32_t tmp = 0, pllmull = 0, pllsource = 0;
\ 00000002 0020 MOVS R0,#+0
\ 00000004 0021 MOVS R1,#+0
\ 00000006 0022 MOVS R2,#+0
248
249 #ifdef STM32F10X_CL
250 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
\ 00000008 0023 MOVS R3,#+0
\ 0000000A 0024 MOVS R4,#+0
\ 0000000C 0025 MOVS R5,#+0
\ 0000000E 0026 MOVS R6,#+0
251 #endif /* STM32F10X_CL */
252
253 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
254 uint32_t prediv1factor = 0;
255 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
256
257 /* Get SYSCLK source -------------------------------------------------------*/
258 tmp = RCC->CFGR & RCC_CFGR_SWS;
\ 00000010 .... LDR.N R7,??DataTable2_1 ;; 0x40021004
\ 00000012 3F68 LDR R7,[R7, #+0]
\ 00000014 17F00C07 ANDS R7,R7,#0xC
\ 00000018 3800 MOVS R0,R7
259
260 switch (tmp)
\ 0000001A 0700 MOVS R7,R0
\ 0000001C 002F CMP R7,#+0
\ 0000001E 04D0 BEQ.N ??SystemCoreClockUpdate_0
\ 00000020 042F CMP R7,#+4
\ 00000022 08D0 BEQ.N ??SystemCoreClockUpdate_1
\ 00000024 082F CMP R7,#+8
\ 00000026 0CD0 BEQ.N ??SystemCoreClockUpdate_2
\ 00000028 54E0 B.N ??SystemCoreClockUpdate_3
261 {
262 case 0x00: /* HSI used as system clock */
263 SystemCoreClock = HSI_VALUE;
\ ??SystemCoreClockUpdate_0:
\ 0000002A .... LDR.N R7,??DataTable2_7
\ 0000002C ........ LDR.W R12,??DataTable2_8 ;; 0x7a1200
\ 00000030 C7F800C0 STR R12,[R7, #+0]
264 break;
\ 00000034 53E0 B.N ??SystemCoreClockUpdate_4
265 case 0x04: /* HSE used as system clock */
266 SystemCoreClock = HSE_VALUE;
\ ??SystemCoreClockUpdate_1:
\ 00000036 .... LDR.N R7,??DataTable2_7
\ 00000038 ........ LDR.W R12,??DataTable2_9 ;; 0x17d7840
\ 0000003C C7F800C0 STR R12,[R7, #+0]
267 break;
\ 00000040 4DE0 B.N ??SystemCoreClockUpdate_4
268 case 0x08: /* PLL used as system clock */
269
270 /* Get PLL clock source and multiplication factor ----------------------*/
271 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
\ ??SystemCoreClockUpdate_2:
\ 00000042 .... LDR.N R7,??DataTable2_1 ;; 0x40021004
\ 00000044 3F68 LDR R7,[R7, #+0]
\ 00000046 17F47017 ANDS R7,R7,#0x3C0000
\ 0000004A 3900 MOVS R1,R7
272 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
\ 0000004C .... LDR.N R7,??DataTable2_1 ;; 0x40021004
\ 0000004E 3F68 LDR R7,[R7, #+0]
\ 00000050 17F48037 ANDS R7,R7,#0x10000
\ 00000054 3A00 MOVS R2,R7
273
274 #ifndef STM32F10X_CL
275 pllmull = ( pllmull >> 18) + 2;
276
277 if (pllsource == 0x00)
278 {
279 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
280 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
281 }
282 else
283 {
284 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
285 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
286 /* HSE oscillator clock selected as PREDIV1 clock entry */
287 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
288 #else
289 /* HSE selected as PLL clock entry */
290 if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
291 {/* HSE oscillator clock divided by 2 */
292 SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
293 }
294 else
295 {
296 SystemCoreClock = HSE_VALUE * pllmull;
297 }
298 #endif
299 }
300 #else
301 pllmull = pllmull >> 18;
\ 00000056 890C LSRS R1,R1,#+18
302
303 if (pllmull != 0x0D)
\ 00000058 0D29 CMP R1,#+13
\ 0000005A 01D0 BEQ.N ??SystemCoreClockUpdate_5
304 {
305 pllmull += 2;
\ 0000005C 891C ADDS R1,R1,#+2
\ 0000005E 01E0 B.N ??SystemCoreClockUpdate_6
306 }
307 else
308 { /* PLL multiplication factor = PLL input clock * 6.5 */
309 pllmull = 13 / 2;
\ ??SystemCoreClockUpdate_5:
\ 00000060 0627 MOVS R7,#+6
\ 00000062 3900 MOVS R1,R7
310 }
311
312 if (pllsource == 0x00)
\ ??SystemCoreClockUpdate_6:
\ 00000064 002A CMP R2,#+0
\ 00000066 07D1 BNE.N ??SystemCoreClockUpdate_7
313 {
314 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
315 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
\ 00000068 .... LDR.N R7,??DataTable2_10 ;; 0x3d0900
\ 0000006A 07FB01F7 MUL R7,R7,R1
\ 0000006E ........ LDR.W R12,??DataTable2_7
\ 00000072 CCF80070 STR R7,[R12, #+0]
\ 00000076 2CE0 B.N ??SystemCoreClockUpdate_8
316 }
317 else
318 {/* PREDIV1 selected as PLL clock entry */
319
320 /* Get PREDIV1 clock source and division factor */
321 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
\ ??SystemCoreClockUpdate_7:
\ 00000078 .... LDR.N R7,??DataTable2_5 ;; 0x4002102c
\ 0000007A 3F68 LDR R7,[R7, #+0]
\ 0000007C 17F48037 ANDS R7,R7,#0x10000
\ 00000080 3B00 MOVS R3,R7
322 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
\ 00000082 .... LDR.N R7,??DataTable2_5 ;; 0x4002102c
\ 00000084 3F68 LDR R7,[R7, #+0]
\ 00000086 17F00F07 ANDS R7,R7,#0xF
\ 0000008A 7F1C ADDS R7,R7,#+1
\ 0000008C 3C00 MOVS R4,R7
323
324 if (prediv1source == 0)
\ 0000008E 002B CMP R3,#+0
\ 00000090 08D1 BNE.N ??SystemCoreClockUpdate_9
325 {
326 /* HSE oscillator clock selected as PREDIV1 clock entry */
327 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
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