system_stm32f10x.lst
来自「stm32+ucos-ii」· LST 代码 · 共 1,249 行 · 第 1/5 页
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528 {
529 HSEStatus = RCC->CR & RCC_CR_HSERDY;
530 StartUpCounter++;
531 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
532
533 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
534 {
535 HSEStatus = (uint32_t)0x01;
536 }
537 else
538 {
539 HSEStatus = (uint32_t)0x00;
540 }
541
542 if (HSEStatus == (uint32_t)0x01)
543 {
544 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
545 /* Enable Prefetch Buffer */
546 FLASH->ACR |= FLASH_ACR_PRFTBE;
547
548 /* Flash 0 wait state */
549 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
550 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
551 #endif
552
553 /* HCLK = SYSCLK */
554 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
555
556 /* PCLK2 = HCLK */
557 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
558
559 /* PCLK1 = HCLK */
560 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
561
562 #ifdef STM32F10X_CL
563 /* Configure PLLs ------------------------------------------------------*/
564 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
565 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
566 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
567 RCC_CFGR_PLLMULL6);
568
569 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
570 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
571 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
572 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
573 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
574 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
575
576 /* Enable PLL2 */
577 RCC->CR |= RCC_CR_PLL2ON;
578 /* Wait till PLL2 is ready */
579 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
580 {
581 }
582 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
583 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
584 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
585 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
586 #else
587 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
588 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
589 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
590 #endif /* STM32F10X_CL */
591
592 /* Enable PLL */
593 RCC->CR |= RCC_CR_PLLON;
594
595 /* Wait till PLL is ready */
596 while((RCC->CR & RCC_CR_PLLRDY) == 0)
597 {
598 }
599
600 /* Select PLL as system clock source */
601 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
602 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
603
604 /* Wait till PLL is used as system clock source */
605 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
606 {
607 }
608 }
609 else
610 { /* If HSE fails to start-up, the application will have wrong clock
611 configuration. User can add here some code to deal with this error */
612 }
613 }
614 #elif defined SYSCLK_FREQ_36MHz
615 /**
616 * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
617 * and PCLK1 prescalers.
618 * @note This function should be used only after reset.
619 * @param None
620 * @retval None
621 */
622 static void SetSysClockTo36(void)
623 {
624 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
625
626 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
627 /* Enable HSE */
628 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
629
630 /* Wait till HSE is ready and if Time out is reached exit */
631 do
632 {
633 HSEStatus = RCC->CR & RCC_CR_HSERDY;
634 StartUpCounter++;
635 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
636
637 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
638 {
639 HSEStatus = (uint32_t)0x01;
640 }
641 else
642 {
643 HSEStatus = (uint32_t)0x00;
644 }
645
646 if (HSEStatus == (uint32_t)0x01)
647 {
648 /* Enable Prefetch Buffer */
649 FLASH->ACR |= FLASH_ACR_PRFTBE;
650
651 /* Flash 1 wait state */
652 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
653 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
654
655 /* HCLK = SYSCLK */
656 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
657
658 /* PCLK2 = HCLK */
659 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
660
661 /* PCLK1 = HCLK */
662 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
663
664 #ifdef STM32F10X_CL
665 /* Configure PLLs ------------------------------------------------------*/
666
667 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
668 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
669 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
670 RCC_CFGR_PLLMULL9);
671
672 /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
673 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
674
675 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
676 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
677 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
678 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
679
680 /* Enable PLL2 */
681 RCC->CR |= RCC_CR_PLL2ON;
682 /* Wait till PLL2 is ready */
683 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
684 {
685 }
686
687 #else
688 /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
689 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
690 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
691 #endif /* STM32F10X_CL */
692
693 /* Enable PLL */
694 RCC->CR |= RCC_CR_PLLON;
695
696 /* Wait till PLL is ready */
697 while((RCC->CR & RCC_CR_PLLRDY) == 0)
698 {
699 }
700
701 /* Select PLL as system clock source */
702 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
703 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
704
705 /* Wait till PLL is used as system clock source */
706 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
707 {
708 }
709 }
710 else
711 { /* If HSE fails to start-up, the application will have wrong clock
712 configuration. User can add here some code to deal with this error */
713 }
714 }
715 #elif defined SYSCLK_FREQ_48MHz
716 /**
717 * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
718 * and PCLK1 prescalers.
719 * @note This function should be used only after reset.
720 * @param None
721 * @retval None
722 */
723 static void SetSysClockTo48(void)
724 {
725 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
726
727 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
728 /* Enable HSE */
729 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
730
731 /* Wait till HSE is ready and if Time out is reached exit */
732 do
733 {
734 HSEStatus = RCC->CR & RCC_CR_HSERDY;
735 StartUpCounter++;
736 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
737
738 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
739 {
740 HSEStatus = (uint32_t)0x01;
741 }
742 else
743 {
744 HSEStatus = (uint32_t)0x00;
745 }
746
747 if (HSEStatus == (uint32_t)0x01)
748 {
749 /* Enable Prefetch Buffer */
750 FLASH->ACR |= FLASH_ACR_PRFTBE;
751
752 /* Flash 1 wait state */
753 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
754 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
755
756 /* HCLK = SYSCLK */
757 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
758
759 /* PCLK2 = HCLK */
760 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
761
762 /* PCLK1 = HCLK */
763 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
764
765 #ifdef STM32F10X_CL
766 /* Configure PLLs ------------------------------------------------------*/
767 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
768 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
769
770 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
771 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
772 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
773 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
774
775 /* Enable PLL2 */
776 RCC->CR |= RCC_CR_PLL2ON;
777 /* Wait till PLL2 is ready */
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