system_stm32f10x.lst
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778 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
779 {
780 }
781
782
783 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
784 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
785 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
786 RCC_CFGR_PLLMULL6);
787 #else
788 /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
789 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
790 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
791 #endif /* STM32F10X_CL */
792
793 /* Enable PLL */
794 RCC->CR |= RCC_CR_PLLON;
795
796 /* Wait till PLL is ready */
797 while((RCC->CR & RCC_CR_PLLRDY) == 0)
798 {
799 }
800
801 /* Select PLL as system clock source */
802 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
803 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
804
805 /* Wait till PLL is used as system clock source */
806 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
807 {
808 }
809 }
810 else
811 { /* If HSE fails to start-up, the application will have wrong clock
812 configuration. User can add here some code to deal with this error */
813 }
814 }
815
816 #elif defined SYSCLK_FREQ_56MHz
817 /**
818 * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
819 * and PCLK1 prescalers.
820 * @note This function should be used only after reset.
821 * @param None
822 * @retval None
823 */
824 static void SetSysClockTo56(void)
825 {
826 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
827
828 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
829 /* Enable HSE */
830 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
831
832 /* Wait till HSE is ready and if Time out is reached exit */
833 do
834 {
835 HSEStatus = RCC->CR & RCC_CR_HSERDY;
836 StartUpCounter++;
837 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
838
839 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
840 {
841 HSEStatus = (uint32_t)0x01;
842 }
843 else
844 {
845 HSEStatus = (uint32_t)0x00;
846 }
847
848 if (HSEStatus == (uint32_t)0x01)
849 {
850 /* Enable Prefetch Buffer */
851 FLASH->ACR |= FLASH_ACR_PRFTBE;
852
853 /* Flash 2 wait state */
854 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
855 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
856
857 /* HCLK = SYSCLK */
858 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
859
860 /* PCLK2 = HCLK */
861 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
862
863 /* PCLK1 = HCLK */
864 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
865
866 #ifdef STM32F10X_CL
867 /* Configure PLLs ------------------------------------------------------*/
868 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
869 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
870
871 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
872 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
873 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
874 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
875
876 /* Enable PLL2 */
877 RCC->CR |= RCC_CR_PLL2ON;
878 /* Wait till PLL2 is ready */
879 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
880 {
881 }
882
883
884 /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
885 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
886 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
887 RCC_CFGR_PLLMULL7);
888 #else
889 /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
890 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
891 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
892
893 #endif /* STM32F10X_CL */
894
895 /* Enable PLL */
896 RCC->CR |= RCC_CR_PLLON;
897
898 /* Wait till PLL is ready */
899 while((RCC->CR & RCC_CR_PLLRDY) == 0)
900 {
901 }
902
903 /* Select PLL as system clock source */
904 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
905 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
906
907 /* Wait till PLL is used as system clock source */
908 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
909 {
910 }
911 }
912 else
913 { /* If HSE fails to start-up, the application will have wrong clock
914 configuration. User can add here some code to deal with this error */
915 }
916 }
917
918 #elif defined SYSCLK_FREQ_72MHz
919 /**
920 * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
921 * and PCLK1 prescalers.
922 * @note This function should be used only after reset.
923 * @param None
924 * @retval None
925 */
\ In section .text, align 2, keep-with-next
926 static void SetSysClockTo72(void)
927 {
\ SetSysClockTo72:
\ 00000000 82B0 SUB SP,SP,#+8
928 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\ 00000002 0020 MOVS R0,#+0
\ 00000004 0190 STR R0,[SP, #+4]
\ 00000006 0020 MOVS R0,#+0
\ 00000008 0090 STR R0,[SP, #+0]
929
930 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
931 /* Enable HSE */
932 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\ 0000000A .... LDR.N R0,??DataTable2 ;; 0x40021000
\ 0000000C 0068 LDR R0,[R0, #+0]
\ 0000000E 50F48030 ORRS R0,R0,#0x10000
\ 00000012 .... LDR.N R1,??DataTable2 ;; 0x40021000
\ 00000014 0860 STR R0,[R1, #+0]
933
934 /* Wait till HSE is ready and if Time out is reached exit */
935 do
936 {
937 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\ ??SetSysClockTo72_0:
\ 00000016 .... LDR.N R0,??DataTable2 ;; 0x40021000
\ 00000018 0068 LDR R0,[R0, #+0]
\ 0000001A 10F40030 ANDS R0,R0,#0x20000
\ 0000001E 0090 STR R0,[SP, #+0]
938 StartUpCounter++;
\ 00000020 0198 LDR R0,[SP, #+4]
\ 00000022 401C ADDS R0,R0,#+1
\ 00000024 0190 STR R0,[SP, #+4]
939 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
\ 00000026 0098 LDR R0,[SP, #+0]
\ 00000028 0028 CMP R0,#+0
\ 0000002A 03D1 BNE.N ??SetSysClockTo72_1
\ 0000002C 0198 LDR R0,[SP, #+4]
\ 0000002E B0F5A06F CMP R0,#+1280
\ 00000032 F0D1 BNE.N ??SetSysClockTo72_0
940
941 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\ ??SetSysClockTo72_1:
\ 00000034 .... LDR.N R0,??DataTable2 ;; 0x40021000
\ 00000036 0068 LDR R0,[R0, #+0]
\ 00000038 8003 LSLS R0,R0,#+14
\ 0000003A 02D5 BPL.N ??SetSysClockTo72_2
942 {
943 HSEStatus = (uint32_t)0x01;
\ 0000003C 0120 MOVS R0,#+1
\ 0000003E 0090 STR R0,[SP, #+0]
\ 00000040 01E0 B.N ??SetSysClockTo72_3
944 }
945 else
946 {
947 HSEStatus = (uint32_t)0x00;
\ ??SetSysClockTo72_2:
\ 00000042 0020 MOVS R0,#+0
\ 00000044 0090 STR R0,[SP, #+0]
948 }
949
950 if (HSEStatus == (uint32_t)0x01)
\ ??SetSysClockTo72_3:
\ 00000046 0098 LDR R0,[SP, #+0]
\ 00000048 0128 CMP R0,#+1
\ 0000004A 5FD1 BNE.N ??SetSysClockTo72_4
951 {
952 /* Enable Prefetch Buffer */
953 FLASH->ACR |= FLASH_ACR_PRFTBE;
\ 0000004C .... LDR.N R0,??DataTable2_12 ;; 0x40022000
\ 0000004E 0068 LDR R0,[R0, #+0]
\ 00000050 50F01000 ORRS R0,R0,#0x10
\ 00000054 .... LDR.N R1,??DataTable2_12 ;; 0x40022000
\ 00000056 0860 STR R0,[R1, #+0]
954
955 /* Flash 2 wait state */
956 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
\ 00000058 .... LDR.N R0,??DataTable2_12 ;; 0x40022000
\ 0000005A 0068 LDR R0,[R0, #+0]
\ 0000005C 8008 LSRS R0,R0,#+2
\ 0000005E 8000 LSLS R0,R0,#+2
\ 00000060 .... LDR.N R1,??DataTable2_12 ;; 0x40022000
\ 00000062 0860 STR R0,[R1, #+0]
957 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
\ 00000064 .... LDR.N R0,??DataTable2_12 ;; 0x40022000
\ 00000066 0068 LDR R0,[R0, #+0]
\ 00000068 50F00200 ORRS R0,R0,#0x2
\ 0000006C .... LDR.N R1,??DataTable2_12 ;; 0x40022000
\ 0000006E 0860 STR R0,[R1, #+0]
958
959
960 /* HCLK = SYSCLK */
961 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\ 00000070 .... LDR.N R0,??DataTable2_1 ;; 0x40021004
\ 00000072 .... LDR.N R1,??DataTable2_1 ;; 0x40021004
\ 00000074 0968 LDR R1,[R1, #+0]
\ 00000076 0160 STR R1,[R0, #+0]
962
963 /* PCLK2 = HCLK */
964 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2⌨️ 快捷键说明
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