system_stm32f10x.lst
来自「stm32+ucos-ii」· LST 代码 · 共 1,249 行 · 第 1/5 页
LST
1,249 行
\ 00000092 .... LDR.N R7,??DataTable2_9 ;; 0x17d7840
\ 00000094 B7FBF4F7 UDIV R7,R7,R4
\ 00000098 4F43 MULS R7,R1,R7
\ 0000009A ........ LDR.W R12,??DataTable2_7
\ 0000009E CCF80070 STR R7,[R12, #+0]
\ 000000A2 16E0 B.N ??SystemCoreClockUpdate_8
328 }
329 else
330 {/* PLL2 clock selected as PREDIV1 clock entry */
331
332 /* Get PREDIV2 division factor and PLL2 multiplication factor */
333 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
\ ??SystemCoreClockUpdate_9:
\ 000000A4 .... LDR.N R7,??DataTable2_5 ;; 0x4002102c
\ 000000A6 3F68 LDR R7,[R7, #+0]
\ 000000A8 C7F30317 UBFX R7,R7,#+4,#+4
\ 000000AC 7F1C ADDS R7,R7,#+1
\ 000000AE 3D00 MOVS R5,R7
334 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
\ 000000B0 .... LDR.N R7,??DataTable2_5 ;; 0x4002102c
\ 000000B2 3F68 LDR R7,[R7, #+0]
\ 000000B4 C7F30327 UBFX R7,R7,#+8,#+4
\ 000000B8 BF1C ADDS R7,R7,#+2
\ 000000BA 3E00 MOVS R6,R7
335 SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
\ 000000BC .... LDR.N R7,??DataTable2_9 ;; 0x17d7840
\ 000000BE B7FBF5F7 UDIV R7,R7,R5
\ 000000C2 7743 MULS R7,R6,R7
\ 000000C4 B7FBF4F7 UDIV R7,R7,R4
\ 000000C8 4F43 MULS R7,R1,R7
\ 000000CA ........ LDR.W R12,??DataTable2_7
\ 000000CE CCF80070 STR R7,[R12, #+0]
336 }
337 }
338 #endif /* STM32F10X_CL */
339 break;
\ ??SystemCoreClockUpdate_8:
\ 000000D2 04E0 B.N ??SystemCoreClockUpdate_4
340
341 default:
342 SystemCoreClock = HSI_VALUE;
\ ??SystemCoreClockUpdate_3:
\ 000000D4 .... LDR.N R7,??DataTable2_7
\ 000000D6 ........ LDR.W R12,??DataTable2_8 ;; 0x7a1200
\ 000000DA C7F800C0 STR R12,[R7, #+0]
343 break;
344 }
345
346 /* Compute HCLK clock frequency ----------------*/
347 /* Get HCLK prescaler */
348 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
\ ??SystemCoreClockUpdate_4:
\ 000000DE .... LDR.N R7,??DataTable2_1 ;; 0x40021004
\ 000000E0 3F68 LDR R7,[R7, #+0]
\ 000000E2 C7F30317 UBFX R7,R7,#+4,#+4
\ 000000E6 ........ LDR.W R12,??DataTable2_11
\ 000000EA 17F80C70 LDRB R7,[R7, R12]
\ 000000EE 3800 MOVS R0,R7
349 /* HCLK clock frequency */
350 SystemCoreClock >>= tmp;
\ 000000F0 .... LDR.N R7,??DataTable2_7
\ 000000F2 3F68 LDR R7,[R7, #+0]
\ 000000F4 C740 LSRS R7,R7,R0
\ 000000F6 ........ LDR.W R12,??DataTable2_7
\ 000000FA CCF80070 STR R7,[R12, #+0]
351 }
\ 000000FE F0BC POP {R4-R7}
\ 00000100 7047 BX LR ;; return
352
353 /**
354 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
355 * @param None
356 * @retval None
357 */
\ In section .text, align 2, keep-with-next
358 static void SetSysClock(void)
359 {
\ SetSysClock:
\ 00000000 80B5 PUSH {R7,LR}
360 #ifdef SYSCLK_FREQ_HSE
361 SetSysClockToHSE();
362 #elif defined SYSCLK_FREQ_24MHz
363 SetSysClockTo24();
364 #elif defined SYSCLK_FREQ_36MHz
365 SetSysClockTo36();
366 #elif defined SYSCLK_FREQ_48MHz
367 SetSysClockTo48();
368 #elif defined SYSCLK_FREQ_56MHz
369 SetSysClockTo56();
370 #elif defined SYSCLK_FREQ_72MHz
371 SetSysClockTo72();
\ 00000002 ........ BL SetSysClockTo72
372 #endif
373
374 /* If none of the define above is enabled, the HSI is used as System clock
375 source (default after reset) */
376 }
\ 00000006 01BD POP {R0,PC} ;; return
377
378 /**
379 * @brief Setup the external memory controller. Called in startup_stm32f10x.s
380 * before jump to __main
381 * @param None
382 * @retval None
383 */
384 #ifdef DATA_IN_ExtSRAM
385 /**
386 * @brief Setup the external memory controller.
387 * Called in startup_stm32f10x_xx.s/.c before jump to main.
388 * This function configures the external SRAM mounted on STM3210E-EVAL
389 * board (STM32 High density devices). This SRAM will be used as program
390 * data memory (including heap and stack).
391 * @param None
392 * @retval None
393 */
394 void SystemInit_ExtMemCtl(void)
395 {
396 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
397 required, then adjust the Register Addresses */
398
399 /* Enable FSMC clock */
400 RCC->AHBENR = 0x00000114;
401
402 /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
403 RCC->APB2ENR = 0x000001E0;
404
405 /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
406 /*---------------- SRAM Address lines configuration -------------------------*/
407 /*---------------- NOE and NWE configuration --------------------------------*/
408 /*---------------- NE3 configuration ----------------------------------------*/
409 /*---------------- NBL0, NBL1 configuration ---------------------------------*/
410
411 GPIOD->CRL = 0x44BB44BB;
412 GPIOD->CRH = 0xBBBBBBBB;
413
414 GPIOE->CRL = 0xB44444BB;
415 GPIOE->CRH = 0xBBBBBBBB;
416
417 GPIOF->CRL = 0x44BBBBBB;
418 GPIOF->CRH = 0xBBBB4444;
419
420 GPIOG->CRL = 0x44BBBBBB;
421 GPIOG->CRH = 0x44444B44;
422
423 /*---------------- FSMC Configuration ---------------------------------------*/
424 /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
425
426 FSMC_Bank1->BTCR[4] = 0x00001011;
427 FSMC_Bank1->BTCR[5] = 0x00000200;
428 }
429 #endif /* DATA_IN_ExtSRAM */
430
431 #ifdef SYSCLK_FREQ_HSE
432 /**
433 * @brief Selects HSE as System clock source and configure HCLK, PCLK2
434 * and PCLK1 prescalers.
435 * @note This function should be used only after reset.
436 * @param None
437 * @retval None
438 */
439 static void SetSysClockToHSE(void)
440 {
441 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
442
443 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
444 /* Enable HSE */
445 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
446
447 /* Wait till HSE is ready and if Time out is reached exit */
448 do
449 {
450 HSEStatus = RCC->CR & RCC_CR_HSERDY;
451 StartUpCounter++;
452 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
453
454 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
455 {
456 HSEStatus = (uint32_t)0x01;
457 }
458 else
459 {
460 HSEStatus = (uint32_t)0x00;
461 }
462
463 if (HSEStatus == (uint32_t)0x01)
464 {
465
466 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
467 /* Enable Prefetch Buffer */
468 FLASH->ACR |= FLASH_ACR_PRFTBE;
469
470 /* Flash 0 wait state */
471 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
472
473 #ifndef STM32F10X_CL
474 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
475 #else
476 if (HSE_VALUE <= 24000000)
477 {
478 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
479 }
480 else
481 {
482 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
483 }
484 #endif /* STM32F10X_CL */
485 #endif
486
487 /* HCLK = SYSCLK */
488 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
489
490 /* PCLK2 = HCLK */
491 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
492
493 /* PCLK1 = HCLK */
494 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
495
496 /* Select HSE as system clock source */
497 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
498 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
499
500 /* Wait till HSE is used as system clock source */
501 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
502 {
503 }
504 }
505 else
506 { /* If HSE fails to start-up, the application will have wrong clock
507 configuration. User can add here some code to deal with this error */
508 }
509 }
510 #elif defined SYSCLK_FREQ_24MHz
511 /**
512 * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
513 * and PCLK1 prescalers.
514 * @note This function should be used only after reset.
515 * @param None
516 * @retval None
517 */
518 static void SetSysClockTo24(void)
519 {
520 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
521
522 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
523 /* Enable HSE */
524 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
525
526 /* Wait till HSE is ready and if Time out is reached exit */
527 do
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