decoder_7seg_new.v

来自「带分频器的bcd计数电路设计」· Verilog 代码 · 共 27 行

module decoder_7seg_new(segment,data);
output[6:0]segment;
input[3:0] data;

reg [6:0] segment;
wire [3:0] data;

always @(data)
begin 
	case(data)
	4'd0: segment[6:0] = 7'b0000001;
	4'd1: segment[6:0] = 7'b1001111;
	4'd2: segment[6:0] = 7'b0010010;
	4'd3: segment[6:0] = 7'b0000110;
	4'd4: segment[6:0] = 7'b1001100;
	4'd5: segment[6:0] = 7'b0100100;
	4'd6: segment[6:0] = 7'b0100000;
	4'd7: segment[6:0] = 7'b0001111;
	4'd8: segment[6:0] = 7'b0000000;
	4'd9: segment[6:0] = 7'b0000100;
	default:
	segment[6:0] = 7'b1111111;
	endcase
end
endmodule