counter_7seg.tan.summary

来自「带分频器的bcd计数电路设计」· SUMMARY 代码 · 共 37 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 18.965 ns
From           : bcd_counter:inst4|low[3]
To             : low[0]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 262.88 MHz ( period = 3.804 ns )
From           : f50MHz_to_1Hz:inst|count1[4]
To             : f50MHz_to_1Hz:inst|count1[6]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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