bcd_counter.v

来自「带分频器的bcd计数电路设计」· Verilog 代码 · 共 34 行

module bcd_counter(cn,high,low,clk,clr);
output[3:0] high,low;
output cn;
input clk,clr;

reg [3:0] high,low;
reg cn;

always@(posedge clk or posedge clr)
if(clr)
	begin 
	high[3:0] =0;
	low[3:0] =0;
	cn = 0;
	end
else
if(low[3:0] == 9)
	begin
	low[3:0] = 0;
	if(high[3:0] == 9)
		begin 
		cn = 1;
		high[3:0] = 0;
		end
	else
		high[3:0] = high[3:0]+1;
end
else
	begin
	low[3:0] = low[3:0]+1;
	cn = 0;
	end		
endmodule