counter_7seg.hier_info

带分频器的bcd计数电路设计

|counter_7seg
cn <= bcd_counter:inst4.cn
clk => f50MHz_to_1Hz:inst.clkin
clr => bcd_counter:inst4.clr
high[0] <= decoder_7seg_new:inst5.segment[0]
high[1] <= decoder_7seg_new:inst5.segment[1]
high[2] <= decoder_7seg_new:inst5.segment[2]
high[3] <= decoder_7seg_new:inst5.segment[3]
high[4] <= decoder_7seg_new:inst5.segment[4]
high[5] <= decoder_7seg_new:inst5.segment[5]
high[6] <= decoder_7seg_new:inst5.segment[6]
low[0] <= decoder_7seg_new:inst6.segment[0]
low[1] <= decoder_7seg_new:inst6.segment[1]
low[2] <= decoder_7seg_new:inst6.segment[2]
low[3] <= decoder_7seg_new:inst6.segment[3]
low[4] <= decoder_7seg_new:inst6.segment[4]
low[5] <= decoder_7seg_new:inst6.segment[5]
low[6] <= decoder_7seg_new:inst6.segment[6]


|counter_7seg|bcd_counter:inst4
cn <= cn~reg0.DB_MAX_OUTPUT_PORT_TYPE
high[0] <= high[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
high[1] <= high[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
high[2] <= high[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
high[3] <= high[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
low[0] <= low[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
low[1] <= low[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
low[2] <= low[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
low[3] <= low[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk => high[2]~reg0.CLK
clk => high[1]~reg0.CLK
clk => high[0]~reg0.CLK
clk => low[3]~reg0.CLK
clk => low[2]~reg0.CLK
clk => low[1]~reg0.CLK
clk => low[0]~reg0.CLK
clk => cn~reg0.CLK
clk => high[3]~reg0.CLK
clr => high[2]~reg0.ACLR
clr => high[1]~reg0.ACLR
clr => high[0]~reg0.ACLR
clr => low[3]~reg0.ACLR
clr => low[2]~reg0.ACLR
clr => low[1]~reg0.ACLR
clr => low[0]~reg0.ACLR
clr => cn~reg0.ACLR
clr => high[3]~reg0.ACLR


|counter_7seg|f50MHz_to_1Hz:inst
clk_1khz <= clk_1khz~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk_1hz <= clk_1hz~reg0.DB_MAX_OUTPUT_PORT_TYPE
clkin => count1[14].CLK
clkin => count1[13].CLK
clkin => count1[12].CLK
clkin => count1[11].CLK
clkin => count1[10].CLK
clkin => count1[9].CLK
clkin => count1[8].CLK
clkin => count1[7].CLK
clkin => count1[6].CLK
clkin => count1[5].CLK
clkin => count1[4].CLK
clkin => count1[3].CLK
clkin => count1[2].CLK
clkin => count1[1].CLK
clkin => count1[0].CLK
clkin => clk_1khz~reg0.CLK
clkin => count1[15].CLK


|counter_7seg|decoder_7seg_new:inst5
segment[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
segment[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
segment[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
segment[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
segment[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
segment[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
segment[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
data[0] => Decoder~0.IN3
data[1] => Decoder~0.IN2
data[2] => Decoder~0.IN1
data[3] => Decoder~0.IN0


|counter_7seg|decoder_7seg_new:inst6
segment[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
segment[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
segment[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
segment[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
segment[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
segment[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
segment[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
data[0] => Decoder~0.IN3
data[1] => Decoder~0.IN2
data[2] => Decoder~0.IN1
data[3] => Decoder~0.IN0