counter_7seg.map.summary

来自「带分频器的bcd计数电路设计」· SUMMARY 代码 · 共 16 行

Flow Status : Successful - Mon Mar 27 11:51:14 2006
Quartus II Version : 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition
Revision Name : counter_7seg
Top-level Entity Name : counter_7seg
Family : Stratix
Device : EP1S10F780C6
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 87
Total pins : 17
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0