f50mhz_to_1hz.v

来自「带分频器的bcd计数电路设计」· Verilog 代码 · 共 27 行

module f50MHz_to_1Hz(clk_1khz, clk_1hz, clkin);
output clk_1khz, clk_1hz;
input clkin;
reg[15:0] count1;
reg[9:0] count2;
reg clk_1khz,clk_1hz;

parameter width = 50000;

always@(posedge clkin)
begin
	if(count1[15:0] == width-1)
		count1[15:0] = 0;
	else
		count1[15:0] = count1[15:0]+1;
	clk_1khz = count1[15];
end
always@(posedge clk_1khz)
begin 
	if(count2[9:0] == 1000-1)
		count2[9:0] = 0;
	else
		count2[9:0] = count2[9:0]+1;
	clk_1hz = count2[9];
end
endmodule