fifo_control.v

在公司做的一个用FPGA实现的数字电视系统中 ASI转TS流的程序

////////////////////////////////////////////////////////////////////////
//File Name:  	fifo_control.v
//SetUp Data: 	2006/03/14
//modify Data:  2006/03/14		Setup the file
//							2006/03/15    modify the file to the style of earlier
//														of fifo.v(2006.3.11)
//Author: 			Shen Zhi
//Function:			Control the fifo_16_8
//
////////////////////////////////////////////////////////////////////////
//`include fifo_16_8.v

//define
`define DEPTH	15			//the number of bytes
`define HALF	8				//half the number of bytes
`define BITS	4				//the bits of depth need
`define WIDTH	8				//the width of one byte

module fifo_control(//input
										reset_n,
										wclk,				//2MHz~27MHz
										rclk,				//27MHz
										din,
										//output
										ena_out,
										dout);
										
parameter address_size = 4;
parameter word_size		 = 8;
parameter mem_size		 = 16;										

input reset_n;
input wclk;
input rclk;
input[word_size-1:0] din;

output ena_out;
output[word_size-1:0] dout;

reg ena;
reg[word_size-1:0] dout;

wire we_n=0;
wire[address_size-1:0] counter;
wire low_thrsh = (counter<=4);              //the bytes' number is less than 4
wire high_thrsh  = (counter>=6);						//more than 8
wire empty			= (counter==0);
wire full				= (counter==16);
wire rd_req			= high_thrsh;

reg  rd_req_d;
reg  rd_req_d2;
reg  ena_d;
reg  rclk_2;

wire[word_size-1:0] fifo_dout;

reg[address_size-1:0] wptr;
reg[address_size-1:0] rptr;

assign  ena_out=rclk_2|ena;
assign	counter=(wptr>=rptr)?wptr-rptr:
					 `DEPTH+wptr-rptr+1;
																				
always@(negedge reset_n or posedge rclk_2)
begin
	if(~reset_n)
	begin
	  rd_req_d  <= 0;
    rd_req_d2 <= 0;
	end
	else
	begin
		rd_req_d  <= rd_req;
    rd_req_d2 <= rd_req_d;
	end
end

always@(negedge reset_n or posedge wclk)				//write data to memory from outside
begin
	if(~reset_n)
	begin
		wptr<=`BITS'b0;
	end
	else
	begin
  	if(wptr>=`DEPTH)
  		wptr<=`BITS'b0;
  	else
  		wptr<=wptr+1;
  	
  	if(counter>=`DEPTH)
  	begin
  		$display("error at time %0t:",$time);
  		$display("FIFO overflow\n");
  	end
  	else;
	end
end

always@(negedge reset_n or posedge rclk_2)						//read data from memory to inside
begin
	if(~reset_n)
	begin
		rptr<=`BITS'b0;
	end
	else if(rd_req_d2)
	begin
    if(rptr>=`DEPTH)
    	rptr<=`BITS'b0;
    else
    	rptr<=rptr+1;
    	
    if(counter==0)
    begin
    	$display("error at time %0t:",$time);
    	$display("FIFO underflow\n");
    end
    else;
  end
end

always@(negedge reset_n or negedge rclk_2)
begin
	if(~reset_n)
	begin
		dout<={`WIDTH{1'bz}};
	end
	else
		dout<=fifo_dout;
end
always@(negedge reset_n or negedge rclk_2)
begin
	if(~reset_n)
	  begin
		ena<=1;
		ena_d<=1;
	  end
	else
	  begin
		ena_d<=~rd_req_d2;
		ena<=ena_d;
	  end
end

always@(negedge reset_n or negedge rclk)
if(~reset_n)
  begin
	rclk_2<=1'b0;
  end
else
  begin
	rclk_2<=~rclk_2;
  end


fifo_16_8 fifo_16_8(
	.wclk	(wclk),
	.rclk (rclk_2),
	.we_n	(we_n),
	.rd(rd_req_d2),
	.wptr (wptr),
	.rptr (rptr),
	.din	(din),
	.dout (fifo_dout)
);

endmodule