fifo_16_8.v

来自「在公司做的一个用FPGA实现的数字电视系统中 ASI转TS流的程序」· Verilog 代码 · 共 53 行

////////////////////////////////////////////////////////////////////////
//File Name:  	FIFO.v
//SetUp Data: 	2006/03/09
//modify Data:  2006/03/09		Setup the file
//							2006/03/14		Rewrite the file.Put the control department
//														outside to module "fifo_control" 
//Author: 			Shen Zhi
//Function:			First input first output,make the two streams between the 
//							input and ouput synchronal
//
////////////////////////////////////////////////////////////////////////

module fifo_16_8(//input
									wclk,rclk,
									we_n,rd,
									wptr,rptr,
									din,
								 //output
								  dout);

parameter address_size = 4;
parameter word_size		 = 8;
parameter mem_size		 = 16;

input wclk;															//write clk
input rclk;															//read clk
input we_n;
input rd;
input[address_size-1:0] wptr;						//write pointer
input[address_size-1:0] rptr;						//read pointer
input[word_size-1:0] din;

output[word_size-1:0] dout;

reg[word_size-1:0] mem [0:mem_size-1];
reg[word_size-1:0] dout;

always@(posedge wclk)
	if(~we_n)	
	begin
		mem[wptr] <= din;
	end
	
always@(posedge rclk)
	if(rd)
	begin
		dout <= mem[rptr];
	end
	else
		dout <= {word_size{1'bz}};
	
endmodule