key_scan1.tan.summary

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.100 ns
From           : rst
To             : div_clk:inst3|clk_scan
From Clock     : 
To Clock       : clk_in
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 32.300 ns
From           : mux1_6:49|out1[0]
To             : segment[6]
From Clock     : clk_in
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.800 ns
From           : diny3
To             : qudou:11|d:17|q
From Clock     : 
To Clock       : clk_in
Failed Paths   : 0

Type           : Clock Setup: 'clk_in'
Slack          : N/A
Required Time  : None
Actual Time    : 74.63 MHz ( period = 13.400 ns )
From           : div_clk:inst3|k[1]
To             : div_clk:inst3|k[31]
From Clock     : clk_in
To Clock       : clk_in
Failed Paths   : 0

Type           : Clock Hold: 'clk_in'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : qudou:6|d:18|q
To             : key_scan:inst|retn_out[0]
From Clock     : clk_in
To Clock       : clk_in
Failed Paths   : 27

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 27

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