📄 mux6_1.rpt
字号:
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\verilog\竞赛\key_scan1\mux6_1.rpt
mux6_1
** EQUATIONS **
cnt00 : INPUT;
cnt01 : INPUT;
cnt02 : INPUT;
cnt03 : INPUT;
cnt10 : INPUT;
cnt11 : INPUT;
cnt12 : INPUT;
cnt13 : INPUT;
cnt20 : INPUT;
cnt21 : INPUT;
cnt22 : INPUT;
cnt23 : INPUT;
cnt30 : INPUT;
cnt31 : INPUT;
cnt32 : INPUT;
cnt33 : INPUT;
cnt40 : INPUT;
cnt41 : INPUT;
cnt42 : INPUT;
cnt43 : INPUT;
cnt50 : INPUT;
cnt51 : INPUT;
cnt52 : INPUT;
cnt53 : INPUT;
sel0 : INPUT;
sel1 : INPUT;
sel2 : INPUT;
-- Node name is 'qout0'
-- Equation name is 'qout0', type is output
qout0 = _LC6_A10;
-- Node name is 'qout1'
-- Equation name is 'qout1', type is output
qout1 = _LC2_A6;
-- Node name is 'qout2'
-- Equation name is 'qout2', type is output
qout2 = _LC6_A6;
-- Node name is 'qout3'
-- Equation name is 'qout3', type is output
qout3 = _LC2_A4;
-- Node name is ':32'
-- Equation name is '_LC2_A10', type is buried
_LC2_A10 = LCELL( _EQ001);
_EQ001 = !sel0 & !sel1 & !sel2;
-- Node name is ':40'
-- Equation name is '_LC3_A10', type is buried
_LC3_A10 = LCELL( _EQ002);
_EQ002 = sel0 & !sel1 & !sel2;
-- Node name is ':48'
-- Equation name is '_LC1_A10', type is buried
_LC1_A10 = LCELL( _EQ003);
_EQ003 = !sel0 & sel1 & !sel2;
-- Node name is ':56'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = LCELL( _EQ004);
_EQ004 = sel0 & sel1 & !sel2;
-- Node name is ':68'
-- Equation name is '_LC6_A4', type is buried
_LC6_A4 = LCELL( _EQ005);
_EQ005 = cnt43 & !sel0 & !sel1 & sel2;
-- Node name is ':69'
-- Equation name is '_LC5_A6', type is buried
_LC5_A6 = LCELL( _EQ006);
_EQ006 = cnt42 & !sel0 & !sel1 & sel2;
-- Node name is ':70'
-- Equation name is '_LC4_A4', type is buried
_LC4_A4 = LCELL( _EQ007);
_EQ007 = cnt41 & !sel0 & !sel1 & sel2;
-- Node name is ':71'
-- Equation name is '_LC5_A10', type is buried
_LC5_A10 = LCELL( _EQ008);
_EQ008 = cnt40 & !sel0 & !sel1 & sel2;
-- Node name is ':76'
-- Equation name is '_LC5_A4', type is buried
_LC5_A4 = LCELL( _EQ009);
_EQ009 = cnt53 & sel0 & !sel1 & sel2;
-- Node name is ':77'
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = LCELL( _EQ010);
_EQ010 = cnt52 & sel0 & !sel1 & sel2;
-- Node name is ':78'
-- Equation name is '_LC3_A4', type is buried
_LC3_A4 = LCELL( _EQ011);
_EQ011 = cnt51 & sel0 & !sel1 & sel2;
-- Node name is ':79'
-- Equation name is '_LC4_A10', type is buried
_LC4_A10 = LCELL( _EQ012);
_EQ012 = cnt50 & sel0 & !sel1 & sel2;
-- Node name is '~90~1'
-- Equation name is '~90~1', location is LC7_A4, type is buried.
-- synthesized logic cell
_LC7_A4 = LCELL( _EQ013);
_EQ013 = cnt03 & _LC2_A10
# _LC5_A4
# _LC6_A4;
-- Node name is '~90~2'
-- Equation name is '~90~2', location is LC8_A4, type is buried.
-- synthesized logic cell
_LC8_A4 = LCELL( _EQ014);
_EQ014 = cnt33 & _LC1_A6
# cnt23 & _LC1_A10;
-- Node name is ':90'
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = LCELL( _EQ015);
_EQ015 = cnt13 & _LC3_A10
# _LC7_A4
# _LC8_A4;
-- Node name is '~91~1'
-- Equation name is '~91~1', location is LC7_A6, type is buried.
-- synthesized logic cell
_LC7_A6 = LCELL( _EQ016);
_EQ016 = cnt02 & _LC2_A10
# _LC4_A6
# _LC5_A6;
-- Node name is '~91~2'
-- Equation name is '~91~2', location is LC8_A6, type is buried.
-- synthesized logic cell
_LC8_A6 = LCELL( _EQ017);
_EQ017 = cnt32 & _LC1_A6
# cnt22 & _LC1_A10;
-- Node name is ':91'
-- Equation name is '_LC6_A6', type is buried
_LC6_A6 = LCELL( _EQ018);
_EQ018 = cnt12 & _LC3_A10
# _LC7_A6
# _LC8_A6;
-- Node name is '~92~1'
-- Equation name is '~92~1', location is LC1_A4, type is buried.
-- synthesized logic cell
_LC1_A4 = LCELL( _EQ019);
_EQ019 = cnt01 & _LC2_A10
# _LC3_A4
# _LC4_A4;
-- Node name is '~92~2'
-- Equation name is '~92~2', location is LC3_A6, type is buried.
-- synthesized logic cell
_LC3_A6 = LCELL( _EQ020);
_EQ020 = cnt31 & _LC1_A6
# cnt21 & _LC1_A10;
-- Node name is ':92'
-- Equation name is '_LC2_A6', type is buried
_LC2_A6 = LCELL( _EQ021);
_EQ021 = cnt11 & _LC3_A10
# _LC1_A4
# _LC3_A6;
-- Node name is '~93~1'
-- Equation name is '~93~1', location is LC7_A10, type is buried.
-- synthesized logic cell
_LC7_A10 = LCELL( _EQ022);
_EQ022 = cnt00 & _LC2_A10
# _LC4_A10
# _LC5_A10;
-- Node name is '~93~2'
-- Equation name is '~93~2', location is LC8_A10, type is buried.
-- synthesized logic cell
_LC8_A10 = LCELL( _EQ023);
_EQ023 = cnt30 & _LC1_A6
# cnt20 & _LC1_A10;
-- Node name is ':93'
-- Equation name is '_LC6_A10', type is buried
_LC6_A10 = LCELL( _EQ024);
_EQ024 = cnt10 & _LC3_A10
# _LC7_A10
# _LC8_A10;
Project Information f:\verilog\竞赛\key_scan1\mux6_1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 88,879K
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