mux6_1.v

来自「用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功」· Verilog 代码 · 共 22 行

module mux6_1(qout,cnt0,cnt1,cnt2,cnt3,cnt4,cnt5,sel);

output[3:0] qout;
input[2:0] sel;
input[3:0] cnt0,cnt1,cnt2,cnt3,cnt4,cnt5;
reg[3:0] qout;

always @(cnt0 or cnt1 or cnt2 or cnt3 or cnt4 or cnt5 or sel)
  begin
  case(sel)
  3'b000: qout=cnt0;
  3'b001: qout=cnt1;
  3'b010: qout=cnt2;
  3'b011: qout=cnt3;
  3'b100: qout=cnt4;
  3'b101: qout=cnt5;
  default: qout=4'bxxxx;
  endcase
  end

endmodule