key_scan1.map.qmsg

用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 05 19:26:11 2005 " "Info: Processing started: Mon Sep 05 19:26:11 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off key_scan1 -c key_scan1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off key_scan1 -c key_scan1" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "com_digit.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file com_digit.v" { { "Info" "ISGN_ENTITY_NAME" "1 com_digit " "Info: Found entity 1: com_digit" {  } { { "com_digit.v" "" { Text "F:/verilog/jingshai/key_scan1/com_digit.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cout6.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cout6.v" { { "Info" "ISGN_ENTITY_NAME" "1 cout6 " "Info: Found entity 1: cout6" {  } { { "cout6.v" "" { Text "F:/verilog/jingshai/key_scan1/cout6.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file d.v" { { "Info" "ISGN_ENTITY_NAME" "1 d " "Info: Found entity 1: d" {  } { { "d.v" "" { Text "F:/verilog/jingshai/key_scan1/d.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decode47.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file decode47.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode47 " "Info: Found entity 1: decode47" {  } { { "decode47.v" "" { Text "F:/verilog/jingshai/key_scan1/decode47.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div_clk.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file div_clk.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_clk " "Info: Found entity 1: div_clk" {  } { { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key_scan.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file key_scan.v" { { "Info" "ISGN_ENTITY_NAME" "1 key_scan " "Info: Found entity 1: key_scan" {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux1_6.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mux1_6.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux1_6 " "Info: Found entity 1: mux1_6" {  } { { "mux1_6.v" "" { Text "F:/verilog/jingshai/key_scan1/mux1_6.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux6_1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mux6_1.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux6_1 " "Info: Found entity 1: mux6_1" {  } { { "mux6_1.v" "" { Text "F:/verilog/jingshai/key_scan1/mux6_1.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key_scan1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file key_scan1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 key_scan1 " "Info: Found entity 1: key_scan1" {  } { { "key_scan1.bdf" "" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "key_scan1 " "Info: Elaborating entity \"key_scan1\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "mux6_1 53 " "Warning: Block or symbol \"mux6_1\" of instance \"53\" overlaps another block or symbol" {  } { { "key_scan1.bdf" "" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { 128 1160 1368 272 "53" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "rst mux1_6 49 " "Warning: Port \"rst\" of type mux1_6 and instance \"49\" is missing source signal" {  } { { "key_scan1.bdf" "" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { 128 944 1136 256 "49" "" } } } }  } 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "clk mux1_6 49 " "Warning: Port \"clk\" of type mux1_6 and instance \"49\" is missing source signal" {  } { { "key_scan1.bdf" "" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { 128 944 1136 256 "49" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "com_digit com_digit:54 " "Info: Elaborating entity \"com_digit\" for hierarchy \"com_digit:54\"" {  } { { "key_scan1.bdf" "54" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { 264 1320 1600 312 "54" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cout6 cout6:inst2 " "Info: Elaborating entity \"cout6\" for hierarchy \"cout6:inst2\"" {  } { { "key_scan1.bdf" "inst2" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { 256 976 1088 352 "inst2" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 cout6.v(11) " "Warning: Verilog HDL assignment warning at cout6.v(11): truncated value with size 32 to match size of target (3)" {  } { { "cout6.v" "" { Text "F:/verilog/jingshai/key_scan1/cout6.v" 11 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_clk div_clk:inst3 " "Info: Elaborating entity \"div_clk\" for hierarchy \"div_clk:inst3\"" {  } { { "key_scan1.bdf" "inst3" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { -24 488 616 72 "inst3" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "clk_qudou div_clk.v(9) " "Info: (10035) Verilog HDL or VHDL information at div_clk.v(9): object \"clk_qudou\" declared but not used" {  } { { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 9 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "j div_clk.v(11) " "Info: (10035) Verilog HDL or VHDL information at div_clk.v(11): object \"j\" declared but not used" {  } { { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 11 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "key_scan key_scan:inst " "Info: Elaborating entity \"key_scan\" for hierarchy \"key_scan:inst\"" {  } { { "key_scan1.bdf" "inst" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { 144 640 864 256 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 key_scan.v(45) " "Warning: Verilog HDL assignment warning at key_scan.v(45): truncated value with size 32 to match size of target (2)" {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 45 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "retn_in0 key_scan.v(65) " "Warning: Verilog HDL Always Construct warning at key_scan.v(65): variable \"retn_in0\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 65 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "retn_in1 key_scan.v(65) " "Warning: Verilog HDL Always Construct warning at key_scan.v(65): variable \"retn_in1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 65 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "retn_in2 key_scan.v(65) " "Warning: Verilog HDL Always Construct warning at key_scan.v(65): variable \"retn_in2\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 65 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "retn_in3 key_scan.v(65) " "Warning: Verilog HDL Always Construct warning at key_scan.v(65): variable \"retn_in3\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 65 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "qout key_scan.v(65) " "Warning: Verilog HDL Always Construct warning at key_scan.v(65): variable \"qout\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 65 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 key_scan.v(65) " "Warning: Verilog HDL assignment warning at key_scan.v(65): truncated value with size 32 to match size of target (1)" {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 65 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 key_scan.v(66) " "Warning: Verilog HDL assignment warning at key_scan.v(66): truncated value with size 32 to match size of target (1)" {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 66 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "qout key_scan.v(63) " "Warning: Verilog HDL Always Construct warning at key_scan.v(63): variable \"qout\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"qout\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "key_scan.v" "" { Text "F:/verilog/jingshai/key_scan1/key_scan.v" 63 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "qudou.gdf 1 1 " "Info: Using design file qudou.gdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 qudou " "Info: Found entity 1: qudou" {  } { { "qudou.gdf" "" { Schematic "F:/verilog/jingshai/key_scan1/qudou.gdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "qudou qudou:6 " "Info: Elaborating entity \"qudou\" for hierarchy \"qudou:6\"" {  } { { "key_scan1.bdf" "6" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { 96 488 600 160 "6" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d qudou:6\|d:17 " "Info: Elaborating entity \"d\" for hierarchy \"qudou:6\|d:17\"" {  } { { "qudou.gdf" "17" { Schematic "F:/verilog/jingshai/key_scan1/qudou.gdf" { { 176 240 344 240 "17" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode47 decode47:37 " "Info: Elaborating entity \"decode47\" for hierarchy \"decode47:37\"" {  } { { "key_scan1.bdf" "37" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { 176 1376 1600 224 "37" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux6_1 mux6_1:53 " "Info: Elaborating entity \"mux6_1\" for hierarchy \"mux6_1:53\"" {  } { { "key_scan1.bdf" "53" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { 128 1160 1368 272 "53" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux1_6 mux1_6:49 " "Info: Elaborating entity \"mux1_6\" for hierarchy \"mux1_6:49\"" {  } { { "key_scan1.bdf" "49" { Schematic "F:/verilog/jingshai/key_scan1/key_scan1.bdf" { { 128 944 1136 256 "49" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quar5.0/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quar5.0/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quar5.0/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quar5.0/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quar5.0/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quar5.0/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quar5.0/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "div_clk.v" "" { Text "F:/verilog/jingshai/key_scan1/div_clk.v" 11 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "254 " "Info: Implemented 254 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "17 " "Info: Implemented 17 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "231 " "Info: Implemented 231 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 05 19:26:16 2005 " "Info: Processing ended: Mon Sep 05 19:26:16 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}